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davemgreendavemgreen
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[ARM] Extra MVE unaligned VLDn tests. NFC
1 parent f3f3c9c commit e841bd5

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4 files changed

+477
-107
lines changed

4 files changed

+477
-107
lines changed

‎llvm/test/CodeGen/Thumb2/mve-vld2.ll

Lines changed: 89 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,23 @@ entry:
9898
ret void
9999
}
100100

101+
define void @vld2_v4i32_align1(<8 x i32> *%src, <4 x i32> *%dst) {
102+
; CHECK-LABEL: vld2_v4i32_align1:
103+
; CHECK: @ %bb.0: @ %entry
104+
; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
105+
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
106+
; CHECK-NEXT: vadd.i32 q0, q0, q1
107+
; CHECK-NEXT: vstrw.32 q0, [r1]
108+
; CHECK-NEXT: bx lr
109+
entry:
110+
%l1 = load <8 x i32>, <8 x i32>* %src, align 1
111+
%s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
112+
%s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
113+
%a = add <4 x i32> %s1, %s2
114+
store <4 x i32> %a, <4 x i32> *%dst
115+
ret void
116+
}
117+
101118
; i16
102119

103120
define void @vld2_v2i16(<4 x i16> *%src, <2 x i16> *%dst) {
@@ -115,7 +132,7 @@ define void @vld2_v2i16(<4 x i16> *%src, <2 x i16> *%dst) {
115132
; CHECK-NEXT: strh r0, [r1]
116133
; CHECK-NEXT: bx lr
117134
entry:
118-
%l1 = load <4 x i16>, <4 x i16>* %src, align 4
135+
%l1 = load <4 x i16>, <4 x i16>* %src, align 2
119136
%s1 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 0, i32 2>
120137
%s2 = shufflevector <4 x i16> %l1, <4 x i16> undef, <2 x i32> <i32 1, i32 3>
121138
%a = add <2 x i16> %s1, %s2
@@ -126,13 +143,13 @@ entry:
126143
define void @vld2_v4i16(<8 x i16> *%src, <4 x i16> *%dst) {
127144
; CHECK-LABEL: vld2_v4i16:
128145
; CHECK: @ %bb.0: @ %entry
129-
; CHECK-NEXT: vldrw.u32 q0, [r0]
146+
; CHECK-NEXT: vldrh.u16 q0, [r0]
130147
; CHECK-NEXT: vrev32.16 q1, q0
131148
; CHECK-NEXT: vadd.i32 q0, q0, q1
132149
; CHECK-NEXT: vstrh.32 q0, [r1]
133150
; CHECK-NEXT: bx lr
134151
entry:
135-
%l1 = load <8 x i16>, <8 x i16>* %src, align 4
152+
%l1 = load <8 x i16>, <8 x i16>* %src, align 2
136153
%s1 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
137154
%s2 = shufflevector <8 x i16> %l1, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
138155
%a = add <4 x i16> %s1, %s2
@@ -149,7 +166,7 @@ define void @vld2_v8i16(<16 x i16> *%src, <8 x i16> *%dst) {
149166
; CHECK-NEXT: vstrw.32 q0, [r1]
150167
; CHECK-NEXT: bx lr
151168
entry:
152-
%l1 = load <16 x i16>, <16 x i16>* %src, align 4
169+
%l1 = load <16 x i16>, <16 x i16>* %src, align 2
153170
%s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
154171
%s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
155172
%a = add <8 x i16> %s1, %s2
@@ -170,14 +187,31 @@ define void @vld2_v16i16(<32 x i16> *%src, <16 x i16> *%dst) {
170187
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
171188
; CHECK-NEXT: bx lr
172189
entry:
173-
%l1 = load <32 x i16>, <32 x i16>* %src, align 4
190+
%l1 = load <32 x i16>, <32 x i16>* %src, align 2
174191
%s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
175192
%s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
176193
%a = add <16 x i16> %s1, %s2
177194
store <16 x i16> %a, <16 x i16> *%dst
178195
ret void
179196
}
180197

198+
define void @vld2_v8i16_align1(<16 x i16> *%src, <8 x i16> *%dst) {
199+
; CHECK-LABEL: vld2_v8i16_align1:
200+
; CHECK: @ %bb.0: @ %entry
201+
; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
202+
; CHECK-NEXT: vld21.16 {q0, q1}, [r0]
203+
; CHECK-NEXT: vadd.i16 q0, q0, q1
204+
; CHECK-NEXT: vstrw.32 q0, [r1]
205+
; CHECK-NEXT: bx lr
206+
entry:
207+
%l1 = load <16 x i16>, <16 x i16>* %src, align 1
208+
%s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
209+
%s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
210+
%a = add <8 x i16> %s1, %s2
211+
store <8 x i16> %a, <8 x i16> *%dst
212+
ret void
213+
}
214+
181215
; i8
182216

183217
define void @vld2_v2i8(<4 x i8> *%src, <2 x i8> *%dst) {
@@ -195,7 +229,7 @@ define void @vld2_v2i8(<4 x i8> *%src, <2 x i8> *%dst) {
195229
; CHECK-NEXT: strb r0, [r1]
196230
; CHECK-NEXT: bx lr
197231
entry:
198-
%l1 = load <4 x i8>, <4 x i8>* %src, align 4
232+
%l1 = load <4 x i8>, <4 x i8>* %src, align 1
199233
%s1 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 0, i32 2>
200234
%s2 = shufflevector <4 x i8> %l1, <4 x i8> undef, <2 x i32> <i32 1, i32 3>
201235
%a = add <2 x i8> %s1, %s2
@@ -212,7 +246,7 @@ define void @vld2_v4i8(<8 x i8> *%src, <4 x i8> *%dst) {
212246
; CHECK-NEXT: vstrb.32 q0, [r1]
213247
; CHECK-NEXT: bx lr
214248
entry:
215-
%l1 = load <8 x i8>, <8 x i8>* %src, align 4
249+
%l1 = load <8 x i8>, <8 x i8>* %src, align 1
216250
%s1 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
217251
%s2 = shufflevector <8 x i8> %l1, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
218252
%a = add <4 x i8> %s1, %s2
@@ -223,13 +257,13 @@ entry:
223257
define void @vld2_v8i8(<16 x i8> *%src, <8 x i8> *%dst) {
224258
; CHECK-LABEL: vld2_v8i8:
225259
; CHECK: @ %bb.0: @ %entry
226-
; CHECK-NEXT: vldrw.u32 q0, [r0]
260+
; CHECK-NEXT: vldrb.u8 q0, [r0]
227261
; CHECK-NEXT: vrev16.8 q1, q0
228262
; CHECK-NEXT: vadd.i16 q0, q0, q1
229263
; CHECK-NEXT: vstrb.16 q0, [r1]
230264
; CHECK-NEXT: bx lr
231265
entry:
232-
%l1 = load <16 x i8>, <16 x i8>* %src, align 4
266+
%l1 = load <16 x i8>, <16 x i8>* %src, align 1
233267
%s1 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
234268
%s2 = shufflevector <16 x i8> %l1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
235269
%a = add <8 x i8> %s1, %s2
@@ -246,7 +280,7 @@ define void @vld2_v16i8(<32 x i8> *%src, <16 x i8> *%dst) {
246280
; CHECK-NEXT: vstrw.32 q0, [r1]
247281
; CHECK-NEXT: bx lr
248282
entry:
249-
%l1 = load <32 x i8>, <32 x i8>* %src, align 4
283+
%l1 = load <32 x i8>, <32 x i8>* %src, align 1
250284
%s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
251285
%s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
252286
%a = add <16 x i8> %s1, %s2
@@ -286,7 +320,7 @@ define void @vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) {
286320
; CHECK-NEXT: vstrw.32 q0, [r1]
287321
; CHECK-NEXT: pop {r4, pc}
288322
entry:
289-
%l1 = load <4 x i64>, <4 x i64>* %src, align 4
323+
%l1 = load <4 x i64>, <4 x i64>* %src, align 8
290324
%s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>
291325
%s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
292326
%a = add <2 x i64> %s1, %s2
@@ -350,7 +384,7 @@ define void @vld2_v4i64(<8 x i64> *%src, <4 x i64> *%dst) {
350384
; CHECK-NEXT: vpop {d8, d9, d10, d11}
351385
; CHECK-NEXT: pop {r4, r5, r6, pc}
352386
entry:
353-
%l1 = load <8 x i64>, <8 x i64>* %src, align 4
387+
%l1 = load <8 x i64>, <8 x i64>* %src, align 8
354388
%s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
355389
%s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
356390
%a = add <4 x i64> %s1, %s2
@@ -452,12 +486,30 @@ entry:
452486
ret void
453487
}
454488

489+
define void @vld2_v4f32_align1(<8 x float> *%src, <4 x float> *%dst) {
490+
; CHECK-LABEL: vld2_v4f32_align1:
491+
; CHECK: @ %bb.0: @ %entry
492+
; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
493+
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]
494+
; CHECK-NEXT: vadd.f32 q0, q0, q1
495+
; CHECK-NEXT: vstrw.32 q0, [r1]
496+
; CHECK-NEXT: bx lr
497+
entry:
498+
%l1 = load <8 x float>, <8 x float>* %src, align 1
499+
%s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
500+
%s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
501+
%a = fadd <4 x float> %s1, %s2
502+
store <4 x float> %a, <4 x float> *%dst
503+
ret void
504+
}
505+
455506
; f16
456507

457508
define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) {
458509
; CHECK-LABEL: vld2_v2f16:
459510
; CHECK: @ %bb.0: @ %entry
460-
; CHECK-NEXT: ldrd r2, r0, [r0]
511+
; CHECK-NEXT: ldr r2, [r0]
512+
; CHECK-NEXT: ldr r0, [r0, #4]
461513
; CHECK-NEXT: vmov.32 q0[0], r2
462514
; CHECK-NEXT: vmov.32 q0[1], r0
463515
; CHECK-NEXT: vmovx.f16 s4, s1
@@ -475,7 +527,7 @@ define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) {
475527
; CHECK-NEXT: str r0, [r1]
476528
; CHECK-NEXT: bx lr
477529
entry:
478-
%l1 = load <4 x half>, <4 x half>* %src, align 4
530+
%l1 = load <4 x half>, <4 x half>* %src, align 2
479531
%s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2>
480532
%s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3>
481533
%a = fadd <2 x half> %s1, %s2
@@ -486,7 +538,7 @@ entry:
486538
define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) {
487539
; CHECK-LABEL: vld2_v4f16:
488540
; CHECK: @ %bb.0: @ %entry
489-
; CHECK-NEXT: vldrw.u32 q0, [r0]
541+
; CHECK-NEXT: vldrh.u16 q0, [r0]
490542
; CHECK-NEXT: vmov r2, s0
491543
; CHECK-NEXT: vmovx.f16 s8, s0
492544
; CHECK-NEXT: vmov r0, s1
@@ -513,7 +565,7 @@ define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) {
513565
; CHECK-NEXT: strd r0, r2, [r1]
514566
; CHECK-NEXT: bx lr
515567
entry:
516-
%l1 = load <8 x half>, <8 x half>* %src, align 4
568+
%l1 = load <8 x half>, <8 x half>* %src, align 2
517569
%s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
518570
%s2 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
519571
%a = fadd <4 x half> %s1, %s2
@@ -530,7 +582,7 @@ define void @vld2_v8f16(<16 x half> *%src, <8 x half> *%dst) {
530582
; CHECK-NEXT: vstrw.32 q0, [r1]
531583
; CHECK-NEXT: bx lr
532584
entry:
533-
%l1 = load <16 x half>, <16 x half>* %src, align 4
585+
%l1 = load <16 x half>, <16 x half>* %src, align 2
534586
%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
535587
%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
536588
%a = fadd <8 x half> %s1, %s2
@@ -551,14 +603,31 @@ define void @vld2_v16f16(<32 x half> *%src, <16 x half> *%dst) {
551603
; CHECK-NEXT: vstrw.32 q2, [r1, #16]
552604
; CHECK-NEXT: bx lr
553605
entry:
554-
%l1 = load <32 x half>, <32 x half>* %src, align 4
606+
%l1 = load <32 x half>, <32 x half>* %src, align 2
555607
%s1 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
556608
%s2 = shufflevector <32 x half> %l1, <32 x half> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
557609
%a = fadd <16 x half> %s1, %s2
558610
store <16 x half> %a, <16 x half> *%dst
559611
ret void
560612
}
561613

614+
define void @vld2_v8f16_align1(<16 x half> *%src, <8 x half> *%dst) {
615+
; CHECK-LABEL: vld2_v8f16_align1:
616+
; CHECK: @ %bb.0: @ %entry
617+
; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
618+
; CHECK-NEXT: vld21.16 {q0, q1}, [r0]
619+
; CHECK-NEXT: vadd.f16 q0, q0, q1
620+
; CHECK-NEXT: vstrw.32 q0, [r1]
621+
; CHECK-NEXT: bx lr
622+
entry:
623+
%l1 = load <16 x half>, <16 x half>* %src, align 1
624+
%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
625+
%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
626+
%a = fadd <8 x half> %s1, %s2
627+
store <8 x half> %a, <8 x half> *%dst
628+
ret void
629+
}
630+
562631
; f64
563632

564633
define void @vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) {
@@ -571,7 +640,7 @@ define void @vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) {
571640
; CHECK-NEXT: vstrw.32 q0, [r1]
572641
; CHECK-NEXT: bx lr
573642
entry:
574-
%l1 = load <4 x double>, <4 x double>* %src, align 4
643+
%l1 = load <4 x double>, <4 x double>* %src, align 8
575644
%s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>
576645
%s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>
577646
%a = fadd <2 x double> %s1, %s2
@@ -594,7 +663,7 @@ define void @vld2_v4f64(<8 x double> *%src, <4 x double> *%dst) {
594663
; CHECK-NEXT: vstrw.32 q1, [r1]
595664
; CHECK-NEXT: bx lr
596665
entry:
597-
%l1 = load <8 x double>, <8 x double>* %src, align 4
666+
%l1 = load <8 x double>, <8 x double>* %src, align 8
598667
%s1 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
599668
%s2 = shufflevector <8 x double> %l1, <8 x double> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
600669
%a = fadd <4 x double> %s1, %s2

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