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HsiangkaiHsiangkai
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[RISCV] Update V extension to v1.0-draft 08a0b464.
Differential Revision: https://reviews.llvm.org/D94583
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8 files changed

+30
-30
lines changed

8 files changed

+30
-30
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
150150
}
151151

152152
if (HasV) {
153-
Builder.defineMacro("__riscv_v", "9000");
153+
Builder.defineMacro("__riscv_v", "1000000");
154154
Builder.defineMacro("__riscv_vector");
155155
}
156156

@@ -191,10 +191,10 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
191191
Builder.defineMacro("__riscv_zfh", "1000");
192192

193193
if (HasZvamo)
194-
Builder.defineMacro("__riscv_zvamo", "9000");
194+
Builder.defineMacro("__riscv_zvamo", "1000000");
195195

196196
if (HasZvlsseg)
197-
Builder.defineMacro("__riscv_zvlsseg", "9000");
197+
Builder.defineMacro("__riscv_zvlsseg", "1000000");
198198
}
199199

200200
/// Return true if has this feature, need to sync with handleTargetFeatures.

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ isExperimentalExtension(StringRef Ext) {
6363
Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
6464
return RISCVExtensionVersion{"0", "93"};
6565
if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
66-
return RISCVExtensionVersion{"0", "9"};
66+
return RISCVExtensionVersion{"1", "0"};
6767
if (Ext == "zfh")
6868
return RISCVExtensionVersion{"0", "1"};
6969
return None;

‎clang/test/Driver/riscv-arch.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,7 @@
384384
// RV32-EXPERIMENTAL-V-BADVERS: error: invalid arch name 'rv32iv0p1'
385385
// RV32-EXPERIMENTAL-V-BADVERS: unsupported version number 0.1 for experimental extension
386386

387-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
387+
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
388388
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
389389
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
390390

@@ -412,7 +412,7 @@
412412
// RV32-EXPERIMENTAL-ZVAMO-BADVERS: error: invalid arch name 'rv32izvamo0p1'
413413
// RV32-EXPERIMENTAL-ZVAMO-BADVERS: unsupported version number 0.1 for experimental extension
414414

415-
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
415+
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
416416
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-GOODVERS %s
417417
// RV32-EXPERIMENTAL-ZVAMO-GOODVERS: "-target-feature" "+experimental-zvamo"
418418

@@ -431,6 +431,6 @@
431431
// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izvlsseg0p1'
432432
// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension
433433

434-
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
434+
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg1p0 -menable-experimental-extensions -### %s -c 2>&1 | \
435435
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
436436
// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -110,23 +110,23 @@
110110
// CHECK-DOUBLE-NOT: __riscv_float_abi_single
111111

112112
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
113-
// RUN: -march=rv32iv0p9 -x c -E -dM %s \
113+
// RUN: -march=rv32iv1p0 -x c -E -dM %s \
114114
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
115115
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
116-
// RUN: -march=rv64iv0p9 -x c -E -dM %s \
116+
// RUN: -march=rv64iv1p0 -x c -E -dM %s \
117117
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
118-
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
118+
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo1p0 -x c -E -dM %s \
119119
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
120-
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo0p9 -x c -E -dM %s \
120+
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvamo1p0 -x c -E -dM %s \
121121
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
122-
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
122+
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg1p0 -x c -E -dM %s \
123123
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
124-
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg0p9 -x c -E -dM %s \
124+
// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv32izvlsseg1p0 -x c -E -dM %s \
125125
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
126-
// CHECK-V-EXT: __riscv_v 9000
126+
// CHECK-V-EXT: __riscv_v 1000000
127127
// CHECK-V-EXT: __riscv_vector 1
128-
// CHECK-V-EXT: __riscv_zvamo 9000
129-
// CHECK-V-EXT: __riscv_zvlsseg 9000
128+
// CHECK-V-EXT: __riscv_zvamo 1000000
129+
// CHECK-V-EXT: __riscv_zvlsseg 1000000
130130

131131
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32izba0p93 -x c -E -dM %s \
132132
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2126,7 +2126,7 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
21262126
if (getFeatureBits(RISCV::FeatureStdExtB))
21272127
formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
21282128
if (getFeatureBits(RISCV::FeatureStdExtV))
2129-
formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
2129+
formalArchStr = (Twine(formalArchStr) + "_v1p0").str();
21302130
if (getFeatureBits(RISCV::FeatureExtZfh))
21312131
formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
21322132
if (getFeatureBits(RISCV::FeatureExtZba))
@@ -2152,9 +2152,9 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
21522152
if (getFeatureBits(RISCV::FeatureExtZbt))
21532153
formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
21542154
if (getFeatureBits(RISCV::FeatureExtZvamo))
2155-
formalArchStr = (Twine(formalArchStr) + "_zvamo0p9").str();
2155+
formalArchStr = (Twine(formalArchStr) + "_zvamo1p0").str();
21562156
if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
2157-
formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p9").str();
2157+
formalArchStr = (Twine(formalArchStr) + "_zvlsseg1p0").str();
21582158

21592159
getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
21602160
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
6363
if (STI.hasFeature(RISCV::FeatureStdExtB))
6464
Arch += "_b0p93";
6565
if (STI.hasFeature(RISCV::FeatureStdExtV))
66-
Arch += "_v0p9";
66+
Arch += "_v1p0";
6767
if (STI.hasFeature(RISCV::FeatureExtZfh))
6868
Arch += "_zfh0p1";
6969
if (STI.hasFeature(RISCV::FeatureExtZba))
@@ -89,9 +89,9 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
8989
if (STI.hasFeature(RISCV::FeatureExtZbt))
9090
Arch += "_zbt0p93";
9191
if (STI.hasFeature(RISCV::FeatureExtZvamo))
92-
Arch += "_zvamo0p9";
92+
Arch += "_zvamo1p0";
9393
if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
94-
Arch += "_zvlsseg0p9";
94+
Arch += "_zvlsseg1p0";
9595

9696
emitTextAttribute(RISCVAttrs::ARCH, Arch);
9797
}

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@
4747
; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
4848
; RV32C: .attribute 5, "rv32i2p0_c2p0"
4949
; RV32B: .attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
50-
; RV32V: .attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
50+
; RV32V: .attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
5151
; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
5252
; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93"
5353
; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93"
@@ -60,7 +60,7 @@
6060
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
6161
; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
6262
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
63-
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
63+
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
6464

6565
; RV64M: .attribute 5, "rv64i2p0_m2p0"
6666
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -80,8 +80,8 @@
8080
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
8181
; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
8282
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
83-
; RV64V: .attribute 5, "rv64i2p0_v0p9_zvamo0p9_zvlsseg0p9"
84-
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p9_zfh0p1_zbb0p93_zvamo0p9_zvlsseg0p9"
83+
; RV64V: .attribute 5, "rv64i2p0_v1p0_zvamo1p0_zvlsseg1p0"
84+
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v1p0_zfh0p1_zbb0p93_zvamo1p0_zvlsseg1p0"
8585

8686

8787
define i32 @addi(i32 %a) {

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
4040
# CHECK: attribute 5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
4141

4242
.attribute arch, "rv32iv"
43-
# CHECK: attribute 5, "rv32i2p0_v0p9"
43+
# CHECK: attribute 5, "rv32i2p0_v1p0"
4444

4545
.attribute arch, "rv32izba"
4646
# CHECK: attribute 5, "rv32i2p0_zba0p93"
@@ -79,7 +79,7 @@
7979
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"
8080

8181
.attribute arch, "rv32ivzvamo_zvlsseg"
82-
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
82+
# CHECK: attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"
8383

84-
.attribute arch, "rv32iv_zvamo0p9_zvlsseg"
85-
# CHECK: attribute 5, "rv32i2p0_v0p9_zvamo0p9_zvlsseg0p9"
84+
.attribute arch, "rv32iv_zvamo1p0_zvlsseg"
85+
# CHECK: attribute 5, "rv32i2p0_v1p0_zvamo1p0_zvlsseg1p0"

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