[SYCL][Joint Matrix][E2E] Add Joint Matrix support and tests for combination 32x32x16 for DG2 (#14753)

Description:
1. The tests are added for testing joint_martix_store,
joint_matrix_load, joint_matrix_apply and joint_matrix_mad for
combination 32x32x16 for SYCL Joint Matrix. These includes Matrix A
bfloat16 32x16 PackedA_RowMajor, Matrix B bfloat16 16x32
PackedB_RowMajor, Matrix B bfloat16 16x32 PackedB_PackedB, Matrix C
float 32x32 Accumulator_RowMajor.
2. Modify sycl/source/detail/device_info.hpp and
sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc
to include the support for combination 32x32x16 for DG2 device.

Author: YixingZhang007

sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc

@@ -1015,12 +1015,13 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
 `architecture::intel_gpu_pvc`
 |8| `architecture::intel_gpu_dg2_g10,
 architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
-.5+|  `matrix_type::bf16`       .5+|  `matrix_type::bf16`   .5+|
+.6+|  `matrix_type::bf16`       .6+|  `matrix_type::bf16`   .6+|
 `matrix_type::fp32`  | 16 | 16 | 16 .4+|`architecture::intel_gpu_pvc`
 | 1 | 64 | 16 | 32 | 64 | 16
 .2+|  +<=+ 8 |  16   .2+|  16
-|8 | `architecture::intel_gpu_dg2_g10,
+|8 .2+| `architecture::intel_gpu_dg2_g10,
 architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
+.1+| 32 .1+| 32 .1+| 16
 |  `matrix_type::tf32`       |  `matrix_type::tf32`   |
 `matrix_type::fp32`   |  +<=+ 8 |  16   |  8 |
 `architecture::intel_gpu_pvc`
@@ -1147,4 +1148,4 @@ load/store overloads
 |11  |2024-04-29 |Yury Plyakhin | Add 1x64x16 supported combination for
 Intel XMX (intel_gpu_pvc)
 |12  |2024-06-14 |Jack Kirk | Add note on sm version device matching issue.
-|======================
+|======================

sycl/source/detail/device_info.hpp

@@ -839,6 +839,8 @@ struct get_device_info_impl<
            matrix_type::fp32, matrix_type::fp32},
           {8, 0, 0, 0, 8, 16, matrix_type::bf16, matrix_type::bf16,
            matrix_type::fp32, matrix_type::fp32},
+          {0, 0, 0, 32, 32, 16, matrix_type::bf16, matrix_type::bf16,
+           matrix_type::fp32, matrix_type::fp32},
       };
     else if (architecture::amd_gpu_gfx90a == DeviceArch)
       return {

sycl/test-e2e/Matrix/element_wise_all_ops_impl.hpp

@@ -240,6 +240,9 @@ int main() {
       test_ewops_ab<bfloat16, 8, 16, use::a, layout::row_major, 1>();
       test_ewops_ab<bfloat16, 16, 8, use::b, layout::ext_intel_packed, 2>();
       test_ewops_c<float, 8, 8>();
+      // test_ewops_ab<bfloat16, 32, 16, use::a, layout::row_major, 1>();
+      // test_ewops_ab<bfloat16, 16, 32, use::b, layout::ext_intel_packed, 2>();
+      // test_ewops_c<float, 32, 32>();
       break;
     }
   }

sycl/test-e2e/Matrix/element_wise_ops_impl.hpp

@@ -142,6 +142,8 @@ int main() {
       passed &= test<uint8_t, int32_t, 8, 8, 32, 4, class dg2_uint_8x8x32>();
       passed &= test<int8_t, int32_t, 8, 8, 32, 4, class dg2_sint_8x8x32>();
       passed &= test<bfloat16, float, 8, 8, 16, 2, class dg2_bf16_8x16x16>();
+      // passed &= test<bfloat16, float, 32, 32, 16, 2, class
+      // dg2_bf16_32x32x16>();
       break;
     }
   }

sycl/test-e2e/Matrix/joint_matrix_bf16_fill_k_cache_impl.hpp

@@ -444,6 +444,8 @@ int main() {
 
       test<bfloat16, float, 2, /*TM*/ 8, /*TN*/ 8, /*TK*/ 16, MCache1, NCache1,
            KCache1, MCache2, NCache2, KCache2>();
+      // test<bfloat16, float, 2, /*TM*/ 32, /*TN*/ 32, /*TK*/ 16, MCache1,
+      //      NCache1, KCache1, MCache2, NCache2, KCache2>();
       break;
     }
   }

sycl/test-e2e/Matrix/joint_matrix_rowmajorA_rowmajorB_impl.hpp

@@ -144,6 +144,8 @@ int main() {
           gemm_row_major<8, 8, 32, class su_8x8x32, int8_t, uint8_t, int32_t>();
       res += gemm_row_major<8, 8, 32, class uu_8x8x32, uint8_t, uint8_t,
                             int32_t>();
+      // res += gemm_row_major<32, 32, 16, class dg2_bf16_32x32x16, bfloat16,
+      //                       bfloat16, float>();
       break;
     }
   }