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[AMDGPU] Write "GFX6-GFX9" instead of "GFX6-9" in docs
... and similarly for some other cases. This is for consistency and to make it easier to search for mentions of a particular architecture. Differential Revision: https://reviews.llvm.org/D95453
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‎llvm/docs/AMDGPUUsage.rst

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -3592,7 +3592,7 @@ The fields used by CP for code objects before V3 also match those specified in
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aligned.
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351:272 20 Reserved, must be 0.
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bytes
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383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-9
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383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-GFX9
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Reserved, must be 0.
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GFX10
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Compute Shader (CS)
@@ -3639,7 +3639,7 @@ The fields used by CP for code objects before V3 also match those specified in
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>454 1 bit ENABLE_SGPR_PRIVATE_SEGMENT
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_SIZE
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457:455 3 bits Reserved, must be 0.
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458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-9
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458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-GFX9
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Reserved, must be 0.
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GFX10
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- If 0 execute in
@@ -3905,7 +3905,7 @@ The fields used by CP for code objects before V3 also match those specified in
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Used by CP to set up
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``COMPUTE_PGM_RSRC1.WGP_MODE``.
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30 1 bit MEM_ORDERED GFX6-9
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30 1 bit MEM_ORDERED GFX6-GFX9
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Reserved, must be 0.
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GFX10
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Controls the behavior of the
@@ -3928,7 +3928,7 @@ The fields used by CP for code objects before V3 also match those specified in
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Used by CP to set up
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``COMPUTE_PGM_RSRC1.MEM_ORDERED``.
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31 1 bit FWD_PROGRESS GFX6-9
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31 1 bit FWD_PROGRESS GFX6-GFX9
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Reserved, must be 0.
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GFX10
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- If 0 execute SIMD wavefronts
@@ -4750,7 +4750,7 @@ in table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
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============ ============ ============== ========== ================================
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LLVM Instr LLVM Memory LLVM Memory AMDGPU AMDGPU Machine Code
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Ordering Sync Scope Address GFX6-9
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Ordering Sync Scope Address GFX6-GFX9
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Space
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============ ============ ============== ========== ================================
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**Non-Atomic**
@@ -8079,41 +8079,41 @@ supports the ``s_trap`` instruction. For usage see:
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.. table:: AMDGPU Trap Handler for AMDHSA OS Code Object V4
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:name: amdgpu-trap-handler-for-amdhsa-os-v4-table
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=================== =============== =============== ============== =======================================
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Usage Code Sequence GFX6-8 Inputs GFX9-10 Inputs Description
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=================== =============== =============== ============== =======================================
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reserved ``s_trap 0x00`` Reserved by hardware.
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debugger breakpoint ``s_trap 0x01`` *none* *none* Reserved for debugger to use for
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breakpoints. Causes wave to be halted
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with the PC at the trap instruction.
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The debugger is responsible to resume
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the wave, including the instruction
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that the breakpoint overwrote.
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``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: *none* Causes wave to be halted with the PC at
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``queue_ptr`` the trap instruction. The associated
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queue is signalled to put it into the
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error state. When the queue is put in
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the error state, the waves executing
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dispatches on the queue will be
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terminated.
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``llvm.debugtrap`` ``s_trap 0x03`` *none* *none* - If debugger not enabled then behaves
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as a no-operation. The trap handler
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is entered and immediately returns to
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continue execution of the wavefront.
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- If the debugger is enabled, causes
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the debug trap to be reported by the
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debugger and the wavefront is put in
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the halt state with the PC at the
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instruction. The debugger must
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increment the PC and resume the wave.
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reserved ``s_trap 0x04`` Reserved.
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reserved ``s_trap 0x05`` Reserved.
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reserved ``s_trap 0x06`` Reserved.
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reserved ``s_trap 0x07`` Reserved.
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reserved ``s_trap 0x08`` Reserved.
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reserved ``s_trap 0xfe`` Reserved.
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reserved ``s_trap 0xff`` Reserved.
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=================== =============== =============== ============== =======================================
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=================== =============== ================ ================= =======================================
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Usage Code Sequence GFX6-GFX8 Inputs GFX9-GFX10 Inputs Description
8084+
=================== =============== ================ ================= =======================================
8085+
reserved ``s_trap 0x00`` Reserved by hardware.
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debugger breakpoint ``s_trap 0x01`` *none* *none* Reserved for debugger to use for
8087+
breakpoints. Causes wave to be halted
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with the PC at the trap instruction.
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The debugger is responsible to resume
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the wave, including the instruction
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that the breakpoint overwrote.
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``llvm.trap`` ``s_trap 0x02`` ``SGPR0-1``: *none* Causes wave to be halted with the PC at
8093+
``queue_ptr`` the trap instruction. The associated
8094+
queue is signalled to put it into the
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error state. When the queue is put in
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the error state, the waves executing
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dispatches on the queue will be
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terminated.
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``llvm.debugtrap`` ``s_trap 0x03`` *none* *none* - If debugger not enabled then behaves
8100+
as a no-operation. The trap handler
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is entered and immediately returns to
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continue execution of the wavefront.
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- If the debugger is enabled, causes
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the debug trap to be reported by the
8105+
debugger and the wavefront is put in
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the halt state with the PC at the
8107+
instruction. The debugger must
8108+
increment the PC and resume the wave.
8109+
reserved ``s_trap 0x04`` Reserved.
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reserved ``s_trap 0x05`` Reserved.
8111+
reserved ``s_trap 0x06`` Reserved.
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reserved ``s_trap 0x07`` Reserved.
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reserved ``s_trap 0x08`` Reserved.
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reserved ``s_trap 0xfe`` Reserved.
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reserved ``s_trap 0xff`` Reserved.
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=================== =============== ================ ================= =======================================
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.. _amdgpu-amdhsa-function-call-convention:
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@@ -8179,7 +8179,7 @@ On entry to a function:
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2. The FLAT_SCRATCH register pair is setup. See
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:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
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3. GFX6-8: M0 register set to the size of LDS in bytes. See
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3. GFX6-GFX8: M0 register set to the size of LDS in bytes. See
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:ref:`amdgpu-amdhsa-kernel-prolog-m0`.
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4. The EXEC register is set to the lanes active on entry to the function.
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5. MODE register: *TBD*
@@ -8237,7 +8237,7 @@ On exit from a function:
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* FLAT_SCRATCH
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* EXEC
8240-
* GFX6-8: M0
8240+
* GFX6-GFX8: M0
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* All SGPR registers except the clobbered registers of SGPR4-31.
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* VGPR40-47
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VGPR56-63

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