We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 48d72fe commit 240a3e4Copy full SHA for 240a3e4
numba_dpcomp/numba_dpcomp/mlir_compiler/lib/pipelines/lower_to_gpu.cpp
@@ -875,11 +875,12 @@ struct AssumeGpuIdRangePass
875
876
mlir::OpBuilder builder(&getContext());
877
builder.setInsertionPointToStart(&op->getRegion(0).front());
878
- auto maxInt = builder
879
- .create<mlir::arith::ConstantIndexOp>(
880
- builder.getUnknownLoc(),
881
- std::numeric_limits<int32_t>::max() + 1)
882
- .getResult();
+ auto maxInt =
+ builder
+ .create<mlir::arith::ConstantIndexOp>(
+ builder.getUnknownLoc(),
+ static_cast<int64_t>(std::numeric_limits<int32_t>::max()) + 1)
883
+ .getResult();
884
885
op->walk([&](mlir::Operation *nestedOp) {
886
if (!mlir::isa<mlir::gpu::ThreadIdOp, mlir::gpu::BlockIdOp,
0 commit comments