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Update llvm version and switch to upstream XeGPU Dialect definition (#736)
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‎build_tools/llvm_version.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
411554a3535e55a1436ccda80064d7a91814dc27
1+
1728a56d0e66c9e64a2e62fa6c5508580ccd28a0

‎build_tools/patches/0001-Add-support-for-VectorAnyINTEL-capability.patch

Lines changed: 112 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From 263d874c1ffcb5b36dca54ecdc148767aadcb7d7 Mon Sep 17 00:00:00 2001
1+
From 94cc2bb6a778cad3b762244d6d78ecf2e19b5372 Mon Sep 17 00:00:00 2001
22
From: Md Abdullah Shahneous Bari <[email protected]>
3-
Date: Thu, 24 Aug 2023 09:05:47 -0700
4-
Subject: [PATCH 1/6] Add support for VectorAnyINTEL capability
3+
Date: Fri, 26 Apr 2024 20:20:28 +0000
4+
Subject: [PATCH 1/7] Add-support-for-VectorAnyINTEL-capability
55

66
Allow vector of any lengths between [2-2^63-1].
77
VectorAnyINTEL capability (part of "SPV_INTEL_vector_compute" extension)
@@ -23,22 +23,26 @@ cases like this. Therefore, for cases like this, enable adding capability
2323
requirement initially, then do the check for capability inferred extension.
2424

2525
- Add support for optionally skipping capability and extension requirement
26+
2627
---
2728
.../mlir/Dialect/SPIRV/IR/SPIRVBase.td | 9 +-
2829
mlir/include/mlir/IR/CommonTypeConstraints.td | 86 ++++++++++++
2930
mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp | 7 +-
3031
mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp | 24 +++-
3132
.../SPIRV/Transforms/SPIRVConversion.cpp | 132 +++++++++++++++---
3233
.../arith-to-spirv-unsupported.mlir | 4 +-
33-
.../ArithToSPIRV/arith-to-spirv.mlir | 35 +++++
34+
.../ArithToSPIRV/arith-to-spirv.mlir | 34 +++++
3435
.../FuncToSPIRV/types-to-spirv.mlir | 17 ++-
36+
.../test/Dialect/SPIRV/IR/arithmetic-ops.mlir | 2 +-
3537
mlir/test/Dialect/SPIRV/IR/bit-ops.mlir | 6 +-
3638
mlir/test/Dialect/SPIRV/IR/gl-ops.mlir | 2 +-
39+
mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir | 4 +-
3740
mlir/test/Dialect/SPIRV/IR/logical-ops.mlir | 2 +-
38-
mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir | 36 ++---
41+
.../Dialect/SPIRV/IR/non-uniform-ops.mlir | 12 +-
42+
mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir | 34 ++---
3943
mlir/test/Target/SPIRV/arithmetic-ops.mlir | 6 +-
4044
mlir/test/Target/SPIRV/ocl-ops.mlir | 6 +
41-
14 files changed, 312 insertions(+), 60 deletions(-)
45+
17 files changed, 319 insertions(+), 68 deletions(-)
4246

4347
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
4448
index 6ec97e17c5dc..75e42c024553 100644
@@ -68,10 +72,10 @@ index 6ec97e17c5dc..75e42c024553 100644
6872
class SPIRV_ScalarOrVectorOf<Type type> :
6973
AnyTypeOf<[type, SPIRV_VectorOf<type>]>;
7074
diff --git a/mlir/include/mlir/IR/CommonTypeConstraints.td b/mlir/include/mlir/IR/CommonTypeConstraints.td
71-
index 03180a687523..e4f2d5562ed7 100644
75+
index af4f13dc0936..28d49d9e91f0 100644
7276
--- a/mlir/include/mlir/IR/CommonTypeConstraints.td
7377
+++ b/mlir/include/mlir/IR/CommonTypeConstraints.td
74-
@@ -604,6 +604,92 @@ class ScalableVectorOfRankAndLengthAndType<list<int> allowedRanks,
78+
@@ -608,6 +608,92 @@ class ScalableVectorOfRankAndLengthAndType<list<int> allowedRanks,
7579
ScalableVectorOfLength<allowedLengths>.summary,
7680
"::mlir::VectorType">;
7781

@@ -165,7 +169,7 @@ index 03180a687523..e4f2d5562ed7 100644
165169
// Negative values for `n` index in reverse.
166170
class ShapedTypeWithNthDimOfSize<int n, list<int> allowedSizes> : Type<
167171
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
168-
index e914f46bdef6..0b139b79f051 100644
172+
index 72488d6e5d0b..b38f20458d32 100644
169173
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
170174
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
171175
@@ -187,9 +187,12 @@ static Type parseAndVerifyType(SPIRVDialect const &dialect,
@@ -226,7 +230,7 @@ index 3f25696aa5eb..2d64fea0dc26 100644
226230
capabilities.push_back(ref);
227231
}
228232
diff --git a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
229-
index 2b79c8022b8e..b778e4f4daf9 100644
233+
index 4072608dc8f8..3fc675632970 100644
230234
--- a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
231235
+++ b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
232236
@@ -43,9 +43,13 @@ using namespace mlir;
@@ -385,7 +389,7 @@ index 2b79c8022b8e..b778e4f4daf9 100644
385389
}
386390

387391
static Type
388-
@@ -1162,16 +1248,18 @@ bool SPIRVConversionTarget::isLegalOp(Operation *op) {
392+
@@ -1163,16 +1249,18 @@ bool SPIRVConversionTarget::isLegalOp(Operation *op) {
389393
SmallVector<ArrayRef<spirv::Extension>, 4> typeExtensions;
390394
SmallVector<ArrayRef<spirv::Capability>, 8> typeCapabilities;
391395
for (Type valueType : valueTypes) {
@@ -430,18 +434,10 @@ index 0d92a8e676d8..d61ace8d6876 100644
430434
}
431435

432436
diff --git a/mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir b/mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
433-
index ae47ae36ca51..0f5e79733574 100644
437+
index ae47ae36ca51..644996fe0fa7 100644
434438
--- a/mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
435439
+++ b/mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
436-
@@ -29,6 +29,7 @@ func.func @int32_scalar(%lhs: i32, %rhs: i32) {
437-
438-
// CHECK-LABEL: @int32_scalar_srem
439-
// CHECK-SAME: (%[[LHS:.+]]: i32, %[[RHS:.+]]: i32)
440-
+ %1 = arith.subi %arg0, %arg0: vector<5xi32>
441-
func.func @int32_scalar_srem(%lhs: i32, %rhs: i32) {
442-
// CHECK: %[[LABS:.+]] = spirv.GL.SAbs %[[LHS]] : i32
443-
// CHECK: %[[RABS:.+]] = spirv.GL.SAbs %[[RHS]] : i32
444-
@@ -1447,6 +1448,40 @@ func.func @ops_flags(%arg0: i64, %arg1: i64) {
440+
@@ -1447,6 +1447,40 @@ func.func @ops_flags(%arg0: i64, %arg1: i64) {
445441
%2 = arith.muli %arg0, %arg1 overflow<nsw, nuw> : i64
446442
// CHECK: %{{.*}} = spirv.IMul %{{.*}}, %{{.*}} : i64
447443
%3 = arith.muli %arg0, %arg1 overflow<nsw, nuw> : i64
@@ -510,6 +506,19 @@ index 82d750755ffe..6f364c5b0875 100644
510506

511507
} // end module
512508

509+
diff --git a/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir b/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir
510+
index 2d0c86e08de5..61fc0b53ed26 100644
511+
--- a/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir
512+
+++ b/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir
513+
@@ -283,7 +283,7 @@ func.func @dot(%arg0: vector<4xf32>, %arg1: vector<4xf32>) -> f16 {
514+
// -----
515+
516+
func.func @dot(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> i32 {
517+
- // expected-error @+1 {{'spirv.Dot' op operand #0 must be vector of 16/32/64-bit float values of length 2/3/4/8/16}}
518+
+ // expected-error @+1 {{op operand #0 must be vector of 16/32/64-bit float values of length 2-9223372036854775807, but got 'vector<4xi32>'}}
519+
%0 = spirv.Dot %arg0, %arg1 : vector<4xi32> -> i32
520+
return %0 : i32
521+
}
513522
diff --git a/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir b/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir
514523
index f3f0ebf60f46..2994b00d582c 100644
515524
--- a/mlir/test/Dialect/SPIRV/IR/bit-ops.mlir
@@ -554,6 +563,28 @@ index 3683e5b469b1..a95a6001fd20 100644
554563
%2 = spirv.GL.Exp %arg0 : vector<5xf32>
555564
return
556565
}
566+
diff --git a/mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir b/mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
567+
index 53a1015de75b..6970b8ec0628 100644
568+
--- a/mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
569+
+++ b/mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir
570+
@@ -21,7 +21,7 @@ spirv.func @f32_to_bf16_vec(%arg0 : vector<2xf32>) "None" {
571+
// -----
572+
573+
spirv.func @f32_to_bf16_unsupported(%arg0 : f64) "None" {
574+
- // expected-error @+1 {{operand #0 must be Float32 or vector of Float32 values of length 2/3/4/8/16, but got}}
575+
+ // expected-error @+1 {{op operand #0 must be Float32 or vector of Float32 values of length 2-9223372036854775807, but got 'f64'}}
576+
%0 = spirv.INTEL.ConvertFToBF16 %arg0 : f64 to i16
577+
spirv.Return
578+
}
579+
@@ -57,7 +57,7 @@ spirv.func @bf16_to_f32_vec(%arg0 : vector<2xi16>) "None" {
580+
// -----
581+
582+
spirv.func @bf16_to_f32_unsupported(%arg0 : i16) "None" {
583+
- // expected-error @+1 {{result #0 must be Float32 or vector of Float32 values of length 2/3/4/8/16, but got}}
584+
+ // expected-error @+1 {{op result #0 must be Float32 or vector of Float32 values of length 2-9223372036854775807, but got 'f16'}}
585+
%0 = spirv.INTEL.ConvertBF16ToF %arg0 : i16 to f16
586+
spirv.Return
587+
}
557588
diff --git a/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir b/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
558589
index 7dc0bd99f54b..5dd9901828cd 100644
559590
--- a/mlir/test/Dialect/SPIRV/IR/logical-ops.mlir
@@ -567,8 +598,66 @@ index 7dc0bd99f54b..5dd9901828cd 100644
567598
%0 = spirv.LogicalNot %arg0 : i32
568599
return
569600
}
601+
diff --git a/mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir b/mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
602+
index f7fd05b36bae..5228bb719d94 100644
603+
--- a/mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
604+
+++ b/mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir
605+
@@ -439,7 +439,7 @@ func.func @group_non_uniform_bitwise_and(%val: i32) -> i32 {
606+
// -----
607+
608+
func.func @group_non_uniform_bitwise_and(%val: i1) -> i1 {
609+
- // expected-error @+1 {{operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2/3/4/8/16, but got 'i1'}}
610+
+ // expected-error @+1 {{op operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2-9223372036854775807, but got 'i1'}}
611+
%0 = spirv.GroupNonUniformBitwiseAnd "Workgroup" "Reduce" %val : i1
612+
return %0: i1
613+
}
614+
@@ -460,7 +460,7 @@ func.func @group_non_uniform_bitwise_or(%val: i32) -> i32 {
615+
// -----
616+
617+
func.func @group_non_uniform_bitwise_or(%val: i1) -> i1 {
618+
- // expected-error @+1 {{operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2/3/4/8/16, but got 'i1'}}
619+
+ // expected-error @+1 {{op operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2-9223372036854775807, but got 'i1'}}
620+
%0 = spirv.GroupNonUniformBitwiseOr "Workgroup" "Reduce" %val : i1
621+
return %0: i1
622+
}
623+
@@ -481,7 +481,7 @@ func.func @group_non_uniform_bitwise_xor(%val: i32) -> i32 {
624+
// -----
625+
626+
func.func @group_non_uniform_bitwise_xor(%val: i1) -> i1 {
627+
- // expected-error @+1 {{operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2/3/4/8/16, but got 'i1'}}
628+
+ // expected-error @+1 {{op operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2-9223372036854775807, but got 'i1'}}
629+
%0 = spirv.GroupNonUniformBitwiseXor "Workgroup" "Reduce" %val : i1
630+
return %0: i1
631+
}
632+
@@ -502,7 +502,7 @@ func.func @group_non_uniform_logical_and(%val: i1) -> i1 {
633+
// -----
634+
635+
func.func @group_non_uniform_logical_and(%val: i32) -> i32 {
636+
- // expected-error @+1 {{operand #0 must be bool or vector of bool values of length 2/3/4/8/16, but got 'i32'}}
637+
+ // expected-error @+1 {{op operand #0 must be bool or vector of bool values of length 2-9223372036854775807, but got 'i32'}}
638+
%0 = spirv.GroupNonUniformLogicalAnd "Workgroup" "Reduce" %val : i32
639+
return %0: i32
640+
}
641+
@@ -523,7 +523,7 @@ func.func @group_non_uniform_logical_or(%val: i1) -> i1 {
642+
// -----
643+
644+
func.func @group_non_uniform_logical_or(%val: i32) -> i32 {
645+
- // expected-error @+1 {{operand #0 must be bool or vector of bool values of length 2/3/4/8/16, but got 'i32'}}
646+
+ // expected-error @+1 {{op operand #0 must be bool or vector of bool values of length 2-9223372036854775807, but got 'i32'}}
647+
%0 = spirv.GroupNonUniformLogicalOr "Workgroup" "Reduce" %val : i32
648+
return %0: i32
649+
}
650+
@@ -544,7 +544,7 @@ func.func @group_non_uniform_logical_xor(%val: i1) -> i1 {
651+
// -----
652+
653+
func.func @group_non_uniform_logical_xor(%val: i32) -> i32 {
654+
- // expected-error @+1 {{operand #0 must be bool or vector of bool values of length 2/3/4/8/16, but got 'i32'}}
655+
+ // expected-error @+1 {{op operand #0 must be bool or vector of bool values of length 2-9223372036854775807, but got 'i32'}}
656+
%0 = spirv.GroupNonUniformLogicalXor "Workgroup" "Reduce" %val : i32
657+
return %0: i32
658+
}
570659
diff --git a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
571-
index 81ba471d3f51..2dbebb2db98e 100644
660+
index 81ba471d3f51..7a29abd44b34 100644
572661
--- a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
573662
+++ b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
574663
@@ -27,7 +27,7 @@ func.func @exp(%arg0 : i32) -> () {
@@ -625,15 +714,7 @@ index 81ba471d3f51..2dbebb2db98e 100644
625714
func.func @sabsi64(%arg0 : i64) -> () {
626715
// CHECK: spirv.CL.s_abs {{%.*}} : i64
627716
%2 = spirv.CL.s_abs %arg0 : i64
628-
@@ -137,21 +145,13 @@ func.func @sabsi8(%arg0 : i8) -> () {
629-
// -----
630-
631-
func.func @sabs(%arg0 : f32) -> () {
632-
- // expected-error @+1 {{op operand #0 must be 8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values}}
633-
+ // expected-error @+1 {{op operand #0 must be 16/32/64-bit float or vector of 16/32/64-bit float values}}
634-
%2 = spirv.CL.s_abs %arg0 : f32
635-
return
636-
}
717+
@@ -144,14 +152,6 @@ func.func @sabs(%arg0 : f32) -> () {
637718

638719
// -----
639720

‎build_tools/patches/0002-change-spirv.CL.printf-op-assembly-format.patch

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From c49e484cae0c62f771ec353bc6fa3113d7b13490 Mon Sep 17 00:00:00 2001
1+
From dc1e914409a9d4c02c21a292227754fa4ac0cea7 Mon Sep 17 00:00:00 2001
22
From: Dimple Prajapati <[email protected]>
3-
Date: Fri, 22 Dec 2023 21:03:10 +0000
4-
Subject: [PATCH 2/6] change spirv.CL.printf op assembly format
3+
Date: Fri, 26 Apr 2024 20:30:34 +0000
4+
Subject: [PATCH 2/7] change-spirv.CL.printf-op-assembly-format
55

66
---
77
mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td | 4 ++--
@@ -31,7 +31,7 @@ index c7c2fe8bc742..b5ca27d7d753 100644
3131

3232
let hasVerifier = 0;
3333
diff --git a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
34-
index 2dbebb2db98e..a7d5f24be296 100644
34+
index 7a29abd44b34..b15ffdbbb767 100644
3535
--- a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
3636
+++ b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
3737
@@ -275,8 +275,8 @@ func.func @rintvec(%arg0 : vector<3xf16>) -> () {
@@ -40,7 +40,7 @@ index 2dbebb2db98e..a7d5f24be296 100644
4040
func.func @printf(%arg0 : !spirv.ptr<i8, UniformConstant>, %arg1 : i32, %arg2 : i32) -> i32 {
4141
- // CHECK: spirv.CL.printf {{%.*}}, {{%.*}}, {{%.*}} : (!spirv.ptr<i8, UniformConstant>, (i32, i32)) -> i32
4242
- %0 = spirv.CL.printf %arg0, %arg1, %arg2 : (!spirv.ptr<i8, UniformConstant>, (i32, i32)) -> i32
43-
+ // CHECK: spirv.CL.printf {{%.*}} : !spirv.ptr<i8, UniformConstant>({{%.*}}, {{%.*}} : (i32, i32)) -> i32
43+
+ // CHECK: spirv.CL.printf {{%.*}} : !spirv.ptr<i8, UniformConstant>({{%.*}}, {{%.*}} : i32, i32) -> i32
4444
+ %0 = spirv.CL.printf %arg0 : !spirv.ptr<i8, UniformConstant>(%arg1, %arg2 : i32, i32) -> i32
4545
return %0 : i32
4646
}

‎build_tools/patches/0003-Add-Constant-attribute-in-ParseDecoration.patch

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,18 @@
1-
From 5a8746dbc8a0853f8bbb7570ed360105970b8894 Mon Sep 17 00:00:00 2001
1+
From 85635423ba70290147e674672854b90bbb81f555 Mon Sep 17 00:00:00 2001
22
From: "Prajapati, Dimple" <[email protected]>
3-
Date: Fri, 12 Jan 2024 09:12:03 -0800
4-
Subject: [PATCH 3/6] Add Constant attribute in ParseDecoration
3+
Date: Fri, 26 Apr 2024 20:32:04 +0000
4+
Subject: [PATCH 3/7] Add-Constant-attribute-in-ParseDecoration
55

66
---
77
mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp | 1 +
88
mlir/lib/Target/SPIRV/Serialization/Serializer.cpp | 1 +
99
2 files changed, 2 insertions(+)
1010

1111
diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
12-
index 02d03b3a0fae..ba3ecc5344bc 100644
12+
index faaa42023a80..cfe3121bbe95 100644
1313
--- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
1414
+++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
15-
@@ -296,6 +296,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
15+
@@ -297,6 +297,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
1616
decorations[words[0]].set(symbol, llvm::dyn_cast<Attribute>(linkageAttr));
1717
break;
1818
}
@@ -21,10 +21,10 @@ index 02d03b3a0fae..ba3ecc5344bc 100644
2121
case spirv::Decoration::AliasedPointer:
2222
case spirv::Decoration::Block:
2323
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
24-
index 40337e007bbf..518facc41e28 100644
24+
index 200abdf993ce..a7d195d7fcb0 100644
2525
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
2626
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
27-
@@ -263,6 +263,7 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
27+
@@ -267,6 +267,7 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
2828
<< stringifyDecoration(decoration);
2929
case spirv::Decoration::Aliased:
3030
case spirv::Decoration::AliasedPointer:

‎build_tools/patches/0004-Add-serialization-and-de-serialization-support-for-s.patch

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
1-
From ab730702ec16bceff41621360172197a73413021 Mon Sep 17 00:00:00 2001
1+
From 1994f9d400c5d768636a89ecf0f78b83431ce609 Mon Sep 17 00:00:00 2001
22
From: Md Abdullah Shahneous Bari <[email protected]>
3-
Date: Mon, 24 Jul 2023 18:25:05 +0000
4-
Subject: [PATCH 4/6] Add serialization and de-serialization support for
3+
Date: Fri, 26 Apr 2024 20:33:41 +0000
4+
Subject: [PATCH 4/7] Add serialization and de-serialization support for
55
several decorations.
66

77
Added decorations:
@@ -18,10 +18,10 @@ Added decorations:
1818
2 files changed, 13 insertions(+), 1 deletion(-)
1919

2020
diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
21-
index ba3ecc5344bc..072672b106f3 100644
21+
index cfe3121bbe95..bc0ca11f4e16 100644
2222
--- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
2323
+++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
24-
@@ -250,8 +250,9 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
24+
@@ -251,8 +251,9 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
2525
symbol, FPFastMathModeAttr::get(opBuilder.getContext(),
2626
static_cast<FPFastMathMode>(words[2])));
2727
break;
@@ -32,18 +32,18 @@ index ba3ecc5344bc..072672b106f3 100644
3232
if (words.size() != 3) {
3333
return emitError(unknownLoc, "OpDecorate with ")
3434
<< decorationName << " needs a single integer literal";
35-
@@ -310,6 +311,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
36-
case spirv::Decoration::RelaxedPrecision:
35+
@@ -312,6 +313,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
3736
case spirv::Decoration::Restrict:
3837
case spirv::Decoration::RestrictPointer:
38+
case spirv::Decoration::NoContraction:
3939
+ case spirv::Decoration::SingleElementVectorINTEL:
4040
+ case spirv::Decoration::VectorComputeCallableFunctionINTEL:
4141
+ case spirv::Decoration::VectorComputeFunctionINTEL:
4242
+ case spirv::Decoration::VectorComputeVariableINTEL:
4343
if (words.size() != 2) {
4444
return emitError(unknownLoc, "OpDecoration with ")
4545
<< decorationName << "needs a single target <id>";
46-
@@ -320,6 +325,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
46+
@@ -322,6 +327,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
4747
// it is needed for many validation rules.
4848
decorations[words[0]].set(symbol, opBuilder.getUnitAttr());
4949
break;
@@ -52,10 +52,10 @@ index ba3ecc5344bc..072672b106f3 100644
5252
case spirv::Decoration::SpecId:
5353
if (words.size() != 3) {
5454
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
55-
index 518facc41e28..9830a0c818e9 100644
55+
index a7d195d7fcb0..34427458d6c1 100644
5656
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
5757
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
58-
@@ -239,8 +239,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
58+
@@ -243,8 +243,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
5959
}
6060
return emitError(loc, "expected FPFastMathModeAttr attribute for ")
6161
<< stringifyDecoration(decoration);
@@ -66,10 +66,10 @@ index 518facc41e28..9830a0c818e9 100644
6666
case spirv::Decoration::Location:
6767
if (auto intAttr = dyn_cast<IntegerAttr>(attr)) {
6868
args.push_back(intAttr.getValue().getZExtValue());
69-
@@ -273,6 +275,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
70-
case spirv::Decoration::RelaxedPrecision:
69+
@@ -278,6 +280,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
7170
case spirv::Decoration::Restrict:
7271
case spirv::Decoration::RestrictPointer:
72+
case spirv::Decoration::NoContraction:
7373
+ case spirv::Decoration::SingleElementVectorINTEL:
7474
+ case spirv::Decoration::VectorComputeCallableFunctionINTEL:
7575
+ case spirv::Decoration::VectorComputeFunctionINTEL:

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