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[LLVM Pulldown] Bump to LLVM rev 228e96b28a84828e1720c387a339a7e68dbd… (#1102)
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42 files changed

+489
-647
lines changed

‎build_tools/llvm_version.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
9f733f4324412ef89cc7729bf027cdcab912ceff
1+
228e96b28a84828e1720c387a339a7e68dbdc029

‎build_tools/patches/0004-Add-serialization-and-de-serialization-support-for-s.patch

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,26 @@
1-
From 4cb4411e2451b1549bafd6a8a3723f78251ef6f3 Mon Sep 17 00:00:00 2001
2-
From: izamyati <[email protected]>
3-
Date: Tue, 1 Oct 2024 08:59:35 -0500
4-
Subject: [PATCH] Add serialization and deserialization support for s
1+
From 89e527e48b727a1479aa47fdbe3d2d178d8969a7 Mon Sep 17 00:00:00 2001
2+
From: Garra1980 <[email protected]>
3+
Date: Mon, 4 Aug 2025 17:50:56 +0200
4+
Subject: [PATCH] Add serilialization and deserialization for spirv
55

66
---
77
mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp | 6 ++++++
88
mlir/lib/Target/SPIRV/Serialization/Serializer.cpp | 6 ++++++
99
2 files changed, 12 insertions(+)
1010

1111
diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
12-
index 6c7fe4106982..b1be812e74eb 100644
12+
index 88931b53a688..f1c22d09cc8e 100644
1313
--- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
1414
+++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
15-
@@ -259,6 +259,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
15+
@@ -282,6 +282,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
1616
symbol, FPRoundingModeAttr::get(opBuilder.getContext(),
1717
static_cast<FPRoundingMode>(words[2])));
1818
break;
1919
+ case spirv::Decoration::Alignment:
2020
case spirv::Decoration::DescriptorSet:
2121
case spirv::Decoration::Binding:
2222
if (words.size() != 3) {
23-
@@ -320,6 +321,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
23+
@@ -343,6 +344,10 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
2424
case spirv::Decoration::RestrictPointer:
2525
case spirv::Decoration::NoContraction:
2626
case spirv::Decoration::Constant:
@@ -31,19 +31,19 @@ index 6c7fe4106982..b1be812e74eb 100644
3131
if (words.size() != 2) {
3232
return emitError(unknownLoc, "OpDecoration with ")
3333
<< decorationName << "needs a single target <id>";
34-
@@ -330,6 +335,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
35-
// it is needed for many validation rules.
36-
decorations[words[0]].set(symbol, opBuilder.getUnitAttr());
34+
@@ -351,6 +356,7 @@ LogicalResult spirv::Deserializer::processDecoration(ArrayRef<uint32_t> words) {
3735
break;
38-
+ case spirv::Decoration::FuncParamIOKindINTEL:
3936
case spirv::Decoration::Location:
4037
case spirv::Decoration::SpecId:
38+
+ case spirv::Decoration::FuncParamIOKindINTEL:
4139
if (words.size() != 3) {
40+
return emitError(unknownLoc, "OpDecoration with ")
41+
<< decorationName << "needs a single integer literal";
4242
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
43-
index f355982e9ed8..d6080185eefe 100644
43+
index 737f29662f64..cd925b02b6a6 100644
4444
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
4545
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
46-
@@ -252,8 +252,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
46+
@@ -283,8 +283,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
4747
}
4848
return emitError(loc, "expected FPRoundingModeAttr attribute for ")
4949
<< stringifyDecoration(decoration);
@@ -54,16 +54,17 @@ index f355982e9ed8..d6080185eefe 100644
5454
case spirv::Decoration::Location:
5555
if (auto intAttr = dyn_cast<IntegerAttr>(attr)) {
5656
args.push_back(intAttr.getValue().getZExtValue());
57-
@@ -287,6 +289,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
57+
@@ -318,6 +320,10 @@ LogicalResult Serializer::processDecorationAttr(Location loc, uint32_t resultID,
5858
case spirv::Decoration::RestrictPointer:
5959
case spirv::Decoration::NoContraction:
6060
case spirv::Decoration::Constant:
6161
+ case spirv::Decoration::SingleElementVectorINTEL:
6262
+ case spirv::Decoration::VectorComputeCallableFunctionINTEL:
6363
+ case spirv::Decoration::VectorComputeFunctionINTEL:
6464
+ case spirv::Decoration::VectorComputeVariableINTEL:
65+
case spirv::Decoration::Block:
6566
// For unit attributes and decoration attributes, the args list
6667
// has no values so we do nothing.
67-
if (isa<UnitAttr, DecorationAttr>(attr))
68-
--
68+
--
6969
2.34.1
70+

‎build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch

Lines changed: 38 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,58 +1,64 @@
1-
From 4e5105ef7e07e8ba312bcfbc7d7b7efe93be2523 Mon Sep 17 00:00:00 2001
1+
From e689c226f0d1cfc3353225e2c9f0c45d307fd960 Mon Sep 17 00:00:00 2001
22
From: Garra1980 <[email protected]>
3-
Date: Tue, 22 Jul 2025 22:46:30 +0200
3+
Date: Tue, 5 Aug 2025 23:19:34 +0200
44
Subject: [PATCH] xegpu temporary downstream defintion changes and vec
55

66
---
77
mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 6 ++++++
8-
mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp | 2 ++
9-
mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp | 3 ++-
10-
3 files changed, 10 insertions(+), 1 deletion(-)
8+
mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp | 7 ++++++-
9+
mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp | 7 ++++---
10+
3 files changed, 16 insertions(+), 4 deletions(-)
1111

1212
diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
13-
index 81e25f7537cb..a7f3367d3774 100644
13+
index 7f4d4f1381df..ebd4f1a3f66a 100644
1414
--- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
1515
+++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
16-
@@ -345,6 +345,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
17-
let arguments = (ins XeGPU_TensorDesc: $TensorDesc,
16+
@@ -373,6 +373,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
17+
OptionalAttr<DenseI64ArrayAttr>: $const_offsets,
1818
OptionalAttr<UnitAttr>: $packed,
1919
OptionalAttr<DenseI64ArrayAttr>: $transpose,
2020
+ OptionalAttr<I32Attr>: $transpose_bit_width,
2121
OptionalAttr<XeGPU_CacheHintAttr>: $l1_hint,
2222
OptionalAttr<XeGPU_CacheHintAttr>: $l2_hint,
2323
OptionalAttr<XeGPU_CacheHintAttr>: $l3_hint);
24-
@@ -971,4 +972,9 @@ def XeGPU_ConvertLayoutOp: XeGPU_Op<"convert_layout", [Pure, AllTypesMatch<["sou
25-
let hasVerifier = 1;
24+
@@ -1147,4 +1148,9 @@ def XeGPU_ConvertLayoutOp: XeGPU_Op<"convert_layout", [Pure, AllTypesMatch<["sou
25+
let hasCanonicalizer = 1;
2626
}
27-
27+
2828
+def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> {
2929
+ let summary = "prevents the compiler from scheduling.";
3030
+ let assemblyFormat = [{ attr-dict }];
3131
+}
3232
+
3333
#endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
3434
diff --git a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
35-
index 80107554144c..b5c013dc5d2d 100644
35+
index 80107554144c..4050a12f2eb8 100644
3636
--- a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
3737
+++ b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
38-
@@ -202,6 +202,7 @@ struct TransferReadLowering : public OpRewritePattern<vector::TransferReadOp> {
38+
@@ -201,7 +201,9 @@ struct TransferReadLowering : public OpRewritePattern<vector::TransferReadOp> {
39+
// By default, no specific caching policy is assigned.
3940
xegpu::CachePolicyAttr hint = nullptr;
4041
auto loadOp = xegpu::LoadNdOp::create(rewriter, loc, vecTy, ndDesc,
42+
+ ValueRange(), DenseI64ArrayAttr(),
4143
/*packed=*/nullptr, transposeAttr,
4244
+ /*transpose_bit_width*/nullptr,
4345
/*l1_hint=*/hint,
4446
/*l2_hint=*/hint, /*l3_hint=*/hint);
4547
rewriter.replaceOp(readOp, loadOp);
46-
@@ -271,6 +272,7 @@ struct LoadLowering : public OpRewritePattern<vector::LoadOp> {
48+
@@ -270,7 +272,10 @@ struct LoadLowering : public OpRewritePattern<vector::LoadOp> {
49+
// By default, no specific caching policy is assigned.
4750
xegpu::CachePolicyAttr hint = nullptr;
4851
auto loadNdOp = xegpu::LoadNdOp::create(
49-
rewriter, loc, vecTy, ndDesc, /*packed=*/nullptr, /*transpose=*/nullptr,
52+
- rewriter, loc, vecTy, ndDesc, /*packed=*/nullptr, /*transpose=*/nullptr,
53+
+ rewriter, loc, vecTy, ndDesc,
54+
+ ValueRange(), DenseI64ArrayAttr(),
55+
+ /*packed=*/nullptr, /*transpose=*/nullptr,
5056
+ /*transpose_bit_width*/nullptr,
5157
/*l1_hint=*/hint,
5258
/*l2_hint=*/hint, /*l3_hint=*/hint);
5359
rewriter.replaceOp(loadOp, loadNdOp);
5460
diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
55-
index c8da5558438e..a4d1e2c344c1 100644
61+
index 33450f3fa229..528b9d55ee61 100644
5662
--- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
5763
+++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
5864
@@ -65,6 +65,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
@@ -62,15 +68,27 @@ index c8da5558438e..a4d1e2c344c1 100644
6268
+ kind == CachePolicy::STREAMING ||
6369
kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
6470
}
65-
66-
@@ -420,7 +421,7 @@ LogicalResult LoadNdOp::verify() {
71+
72+
@@ -419,8 +420,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
73+
xegpu::CachePolicyAttr l3_hint) {
74+
75+
return build(builder, state, retType, tensorDesc, ValueRange(),
76+
- DenseI64ArrayAttr(), packed, transpose, l1_hint, l2_hint,
77+
- l3_hint);
78+
+ DenseI64ArrayAttr(), packed, transpose, nullptr,
79+
+ l1_hint, l2_hint, l3_hint);
80+
}
81+
82+
LogicalResult LoadNdOp::verify() {
83+
@@ -482,7 +483,7 @@ LogicalResult LoadNdOp::verify() {
6784
mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored.";
6885
}
69-
86+
7087
- if (getPacked()) {
7188
+ if (getPacked() || getTransposeBitWidth() == 32) {
7289
if (tdescTy.getRank() == 2) {
7390
const int axis = 0;
7491
auto vnni_factor = valueShape.back();
75-
--
92+
--
7693
2.34.1
94+

‎include/imex/Dialect/NDArray/Transforms/Passes.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ def CoalesceShardOps : Pass<"coalesce-shard-ops"> {
4141
subview operations.
4242
}];
4343
let constructor = "imex::createCoalesceShardOpsPass()";
44-
let dependentDialects = ["::mlir::mesh::MeshDialect",
44+
let dependentDialects = ["::mlir::shard::ShardDialect",
4545
"::mlir::arith::ArithDialect",
4646
"::mlir::tensor::TensorDialect",
4747
"::mlir::memref::MemRefDialect"];

‎lib/Conversion/XeGPUToVC/LSCPatterns.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1145,7 +1145,7 @@ class LoadGatherPattern : public OpConversionPattern<LoadGatherOp> {
11451145
auto resultTy = cast<VectorType>(op.getType());
11461146
auto newValue = genLoadIntrinsicCallWithC32BConversion(
11471147
rewriter, loc, resultTy, simd_lanes, op.getMask(), l1hint, l3hint,
1148-
elemTy, chunkSize, tdescTy.getMemorySpace(), adaptor.getTensorDesc());
1148+
elemTy, chunkSize, tdescTy.getMemorySpace(), adaptor.getSource());
11491149

11501150
// transpose the result because of the difference between hardware
11511151
// implementation and the XeGPU definition.
@@ -1200,7 +1200,7 @@ class PrefetchPattern : public OpConversionPattern<PrefetchOp> {
12001200

12011201
auto callOp = genPrefetchIntrinsicCall(rewriter, loc, simd_lanes, l1hint,
12021202
l3hint, elemTy, chunkSize, scope,
1203-
adaptor.getTensorDesc());
1203+
adaptor.getSource());
12041204

12051205
rewriter.replaceOp(op, callOp);
12061206
return success();
@@ -1257,7 +1257,7 @@ class StoreScatterPattern : public OpConversionPattern<StoreScatterOp> {
12571257
}
12581258
auto callOp = genStoreIntrinsicCallWithC32BConversion(
12591259
rewriter, loc, simd_lanes, op.getMask(), l1hint, l3hint, elemTy,
1260-
chunkSize, tdescTy.getMemorySpace(), adaptor.getTensorDesc(), data);
1260+
chunkSize, tdescTy.getMemorySpace(), adaptor.getDest(), data);
12611261

12621262
rewriter.replaceOp(op, callOp);
12631263
return success();

‎lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -461,20 +461,24 @@ class LoadStoreToXeVMPattern : public OpConversionPattern<OpType> {
461461
auto tdesc = op.getTensorDescType();
462462
auto ptrTypeLLVM = LLVM::LLVMPointerType::get(
463463
ctxt, getNumericXeVMAddrSpace(tdesc.getMemorySpace()));
464-
Value basePtrI64 = rewriter.create<arith::IndexCastOp>(
465-
loc, rewriter.getI64Type(), adaptor.getTensorDesc());
466-
Value basePtrLLVM =
467-
rewriter.create<LLVM::IntToPtrOp>(loc, ptrTypeLLVM, basePtrI64);
468464
VectorType srcOrDstVecTy = cast<VectorType>(op.getValue().getType());
469465
VectorType srcOrDstFlatVecTy = VectorType::get(
470466
srcOrDstVecTy.getNumElements(), srcOrDstVecTy.getElementType());
471467
if constexpr (std::is_same_v<OpType, LoadGatherOp>) {
468+
Value basePtrI64 = rewriter.create<arith::IndexCastOp>(
469+
loc, rewriter.getI64Type(), adaptor.getSource());
470+
Value basePtrLLVM =
471+
rewriter.create<LLVM::IntToPtrOp>(loc, ptrTypeLLVM, basePtrI64);
472472
Value loaded =
473473
rewriter.create<LLVM::LoadOp>(loc, srcOrDstFlatVecTy, basePtrLLVM);
474474
auto newOp =
475475
rewriter.create<vector::ShapeCastOp>(loc, srcOrDstVecTy, loaded);
476476
rewriter.replaceOp(op, newOp);
477477
} else {
478+
Value basePtrI64 = rewriter.create<arith::IndexCastOp>(
479+
loc, rewriter.getI64Type(), adaptor.getDest());
480+
Value basePtrLLVM =
481+
rewriter.create<LLVM::IntToPtrOp>(loc, ptrTypeLLVM, basePtrI64);
478482
Value srcFlatVec = rewriter.create<vector::ShapeCastOp>(
479483
loc, srcOrDstFlatVecTy, op.getValue());
480484
rewriter.create<LLVM::StoreOp>(loc, srcFlatVec, basePtrLLVM);
@@ -495,7 +499,7 @@ class PrefetchToXeVMPattern : public OpConversionPattern<xegpu::PrefetchOp> {
495499
auto ptrTypeLLVM = LLVM::LLVMPointerType::get(
496500
ctxt, getNumericXeVMAddrSpace(tdescTy.getMemorySpace()));
497501
Value basePtrI64 = rewriter.create<arith::IndexCastOp>(
498-
loc, rewriter.getI64Type(), adaptor.getTensorDesc());
502+
loc, rewriter.getI64Type(), adaptor.getSource());
499503
Value ptrLLVM =
500504
rewriter.create<LLVM::IntToPtrOp>(loc, ptrTypeLLVM, basePtrI64);
501505
rewriter.create<xevm::PrefetchOp>(

‎lib/Conversion/XeTileToXeGPU/XeTileToXeGPU.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,7 @@ class LoadOpPattern : public OpConversionPattern<xetile::LoadTileOp> {
492492
auto transAttr = DenseI64ArrayAttr();
493493
auto bitWidthAttr = IntegerAttr();
494494
auto ldOp = rewriter.create<xegpu::LoadNdOp>(loc, vecTy, adaptor.getTile(),
495+
ValueRange(), DenseI64ArrayAttr(),
495496
packAttr, transAttr,
496497
bitWidthAttr, L1, L2, L3);
497498

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