Merge pull request #4 from dchigarev/llvm_upd

Update LLVM

Author: Menooker

build_tools/llvm_version.txt

@@ -1 +1 @@
-08a61eb01172054fc5f8c78ff527f01d9768569b
+f06563a5c0d239a6b98f74db522681613254ad08

build_tools/patches/0001-Add-support-for-VectorAnyINTEL-capability.patch

@@ -45,10 +45,10 @@ requirement initially, then do the check for capability inferred extension.
  17 files changed, 319 insertions(+), 68 deletions(-)
 
 diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
-index 6ec97e17c5dc..75e42c024553 100644
+index af0b2624feb3..b6e80c3f9516 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
 +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
-@@ -4138,7 +4138,12 @@ def SPIRV_Int32 : TypeAlias<I32, "Int32">;
+@@ -4142,7 +4142,12 @@ def SPIRV_Int32 : TypeAlias<I32, "Int32">;
  def SPIRV_Float32 : TypeAlias<F32, "Float32">;
  def SPIRV_Float : FloatOfWidths<[16, 32, 64]>;
  def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>;
@@ -62,8 +62,8 @@ index 6ec97e17c5dc..75e42c024553 100644
                                         [SPIRV_Bool, SPIRV_Integer, SPIRV_Float]>;
  // Component type check is done in the type parser for the following SPIR-V
  // dialect-specific types so we use "Any" here.
-@@ -4189,7 +4194,7 @@ class SPIRV_JointMatrixOfType<list<Type> allowedTypes> :
-     "Joint Matrix">;
+@@ -4185,7 +4190,7 @@ class SPIRV_CoopMatrixOfType<list<Type> allowedTypes> :
+     "Cooperative Matrix">;
 
  class SPIRV_VectorOf<Type type> :
 -    VectorOfLengthAndType<[2, 3, 4, 8,16], [type]>;
@@ -764,4 +764,4 @@ index 9a2e4cf62e37..31a7f616d648 100644
      // CHECK: spirv.CL.fma {{%[^,]*}}, {{%[^,]*}}, {{%[^,]*}} : f32
      %13 = spirv.CL.fma %arg0, %arg1, %arg2 : f32
 --
-2.34.1
+2.34.1

build_tools/patches/0009-SPIR-V-Enable-native-bf16-support-in-SPIR-V-dialect.patch

@@ -21,63 +21,63 @@ index 22d5afcd7738..de9e11493793 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
 +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
 @@ -82,7 +82,7 @@ class SPIRV_ArithmeticExtendedBinaryOp<string mnemonic,
-
+ 
  // -----
-
+ 
 -def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_Float, [Commutative]> {
 +def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_AnyFloat, [Commutative]> {
    let summary = "Floating-point addition of Operand 1 and Operand 2.";
-
+ 
    let description = [{
 @@ -104,7 +104,7 @@ def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_Float, [Commutative]>
-
+ 
  // -----
-
+ 
 -def SPIRV_FDivOp : SPIRV_ArithmeticBinaryOp<"FDiv", SPIRV_Float, []> {
 +def SPIRV_FDivOp : SPIRV_ArithmeticBinaryOp<"FDiv", SPIRV_AnyFloat, []> {
    let summary = "Floating-point division of Operand 1 divided by Operand 2.";
-
+ 
    let description = [{
 @@ -154,7 +154,7 @@ def SPIRV_FModOp : SPIRV_ArithmeticBinaryOp<"FMod", SPIRV_Float, []> {
-
+ 
  // -----
-
+ 
 -def SPIRV_FMulOp : SPIRV_ArithmeticBinaryOp<"FMul", SPIRV_Float, [Commutative]> {
 +def SPIRV_FMulOp : SPIRV_ArithmeticBinaryOp<"FMul", SPIRV_AnyFloat, [Commutative]> {
    let summary = "Floating-point multiplication of Operand 1 and Operand 2.";
-
+ 
    let description = [{
 @@ -229,7 +229,7 @@ def SPIRV_FRemOp : SPIRV_ArithmeticBinaryOp<"FRem", SPIRV_Float, []> {
-
+ 
  // -----
-
+ 
 -def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOp<"FSub", SPIRV_Float, []> {
 +def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOp<"FSub", SPIRV_AnyFloat, []> {
    let summary = "Floating-point subtraction of Operand 2 from Operand 1.";
-
+ 
    let description = [{
 @@ -450,7 +450,7 @@ def SPIRV_DotOp : SPIRV_Op<"Dot",
    );
-
+ 
    let results = (outs
 -    SPIRV_Float:$result
 +    SPIRV_AnyFloat:$result
    );
-
+ 
    let assemblyFormat = "operands attr-dict `:` type($vector1) `->` type($result)";
 diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
-index 04952dd1dc61..6c9c348490ab 100644
+index ddaeb13ef253..336bdcfb7a48 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
 +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
 @@ -343,6 +343,7 @@ def SPV_KHR_subgroup_rotate                  : I32EnumAttrCase<"SPV_KHR_subgroup
  def SPV_KHR_non_semantic_info                : I32EnumAttrCase<"SPV_KHR_non_semantic_info", 29>;
  def SPV_KHR_terminate_invocation             : I32EnumAttrCase<"SPV_KHR_terminate_invocation", 30>;
  def SPV_KHR_cooperative_matrix               : I32EnumAttrCase<"SPV_KHR_cooperative_matrix", 31>;
 +def SPV_KHR_bfloat16                         : I32EnumAttrCase<"SPV_KHR_bfloat16", 32>;
-
+ 
  def SPV_EXT_demote_to_helper_invocation  : I32EnumAttrCase<"SPV_EXT_demote_to_helper_invocation", 1000>;
  def SPV_EXT_descriptor_indexing          : I32EnumAttrCase<"SPV_EXT_descriptor_indexing", 1001>;
-@@ -435,7 +436,7 @@ def SPIRV_ExtensionAttr :
+@@ -434,7 +435,7 @@ def SPIRV_ExtensionAttr :
        SPV_KHR_fragment_shader_barycentric, SPV_KHR_ray_cull_mask,
        SPV_KHR_uniform_group_instructions, SPV_KHR_subgroup_rotate,
        SPV_KHR_non_semantic_info, SPV_KHR_terminate_invocation,
@@ -86,7 +86,7 @@ index 04952dd1dc61..6c9c348490ab 100644
        SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_indexing,
        SPV_EXT_fragment_fully_covered, SPV_EXT_fragment_invocation_density,
        SPV_EXT_fragment_shader_interlock, SPV_EXT_physical_storage_buffer,
-@@ -1193,6 +1194,22 @@ def SPIRV_C_ShaderClockKHR                              : I32EnumAttrCase<"Shade
+@@ -1192,6 +1193,24 @@ def SPIRV_C_ShaderClockKHR                              : I32EnumAttrCase<"Shade
      Extension<[SPV_KHR_shader_clock]>
    ];
  }
@@ -95,11 +95,13 @@ index 04952dd1dc61..6c9c348490ab 100644
 +    Extension<[SPV_KHR_bfloat16]>
 +  ];
 +}
++
 +def SPIRV_C_BFloat16DotProductKHR                              : I32EnumAttrCase<"BFloat16DotProductKHR", 5117> {
 +  list<I32EnumAttrCase> implies = [SPIRV_C_BFloat16TypeKHR];
 +  list<Availability> availability = [
 +    Extension<[SPV_KHR_bfloat16]>  ];
 +}
++
 +def SPIRV_C_BFloat16CooperativeMatrixKHR                              : I32EnumAttrCase<"BFloat16CooperativeMatrixKHR", 5118> {
 +  list<I32EnumAttrCase> implies = [SPIRV_C_BFloat16TypeKHR, SPIRV_C_CooperativeMatrixKHR];
 +  list<Availability> availability = [
@@ -109,15 +111,15 @@ index 04952dd1dc61..6c9c348490ab 100644
  def SPIRV_C_FragmentFullyCoveredEXT                     : I32EnumAttrCase<"FragmentFullyCoveredEXT", 5265> {
    list<I32EnumAttrCase> implies = [SPIRV_C_Shader];
    list<Availability> availability = [
-@@ -1491,6 +1508,7 @@ def SPIRV_CapabilityAttr :
+@@ -1484,6 +1503,7 @@ def SPIRV_CapabilityAttr :
        SPIRV_C_RayQueryKHR, SPIRV_C_RayTracingKHR, SPIRV_C_Float16ImageAMD,
        SPIRV_C_ImageGatherBiasLodAMD, SPIRV_C_FragmentMaskAMD, SPIRV_C_StencilExportEXT,
        SPIRV_C_ImageReadWriteLodAMD, SPIRV_C_Int64ImageEXT, SPIRV_C_ShaderClockKHR,
 +      SPIRV_C_BFloat16TypeKHR, SPIRV_C_BFloat16DotProductKHR, SPIRV_C_BFloat16CooperativeMatrixKHR,
        SPIRV_C_FragmentFullyCoveredEXT, SPIRV_C_MeshShadingNV, SPIRV_C_FragmentDensityEXT,
        SPIRV_C_ShaderNonUniform, SPIRV_C_RuntimeDescriptorArray,
        SPIRV_C_StorageTexelBufferArrayDynamicIndexing, SPIRV_C_RayTracingNV,
-@@ -4148,16 +4166,21 @@ def SPIRV_Bool : TypeAlias<I1, "bool">;
+@@ -4139,16 +4159,21 @@ def SPIRV_Bool : TypeAlias<I1, "bool">;
  def SPIRV_Integer : AnyIntOfWidths<[8, 16, 32, 64]>;
  def SPIRV_Int16 : TypeAlias<I16, "Int16">;
  def SPIRV_Int32 : TypeAlias<I32, "Int32">;
@@ -142,36 +144,34 @@ index 04952dd1dc61..6c9c348490ab 100644
  // Component type check is done in the type parser for the following SPIR-V
  // dialect-specific types so we use "Any" here.
  def SPIRV_AnyPtr : DialectType<SPIRV_Dialect, SPIRV_IsPtrType,
-@@ -4180,14 +4203,14 @@ def SPIRV_AnyStruct : DialectType<SPIRV_Dialect, SPIRV_IsStructType,
+@@ -4169,14 +4194,14 @@ def SPIRV_AnyStruct : DialectType<SPIRV_Dialect, SPIRV_IsStructType,
  def SPIRV_AnySampledImage : DialectType<SPIRV_Dialect, SPIRV_IsSampledImageType,
                                  "any SPIR-V sampled image type">;
-
+ 
 -def SPIRV_Numerical : AnyTypeOf<[SPIRV_Integer, SPIRV_Float]>;
 +def SPIRV_Numerical : AnyTypeOf<[SPIRV_Integer, SPIRV_Float, SPIRV_BFloat16KHR]>;
  def SPIRV_Scalar : AnyTypeOf<[SPIRV_Numerical, SPIRV_Bool]>;
  def SPIRV_Aggregate : AnyTypeOf<[SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct]>;
  def SPIRV_Composite :
      AnyTypeOf<[SPIRV_Vector, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct,
-                SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix]>;
+                SPIRV_AnyCooperativeMatrix, SPIRV_AnyMatrix]>;
  def SPIRV_Type : AnyTypeOf<[
 -    SPIRV_Void, SPIRV_Bool, SPIRV_Integer, SPIRV_Float, SPIRV_Vector,
 +    SPIRV_Void, SPIRV_Bool, SPIRV_Integer, SPIRV_Float, SPIRV_BFloat16KHR, SPIRV_Vector,
      SPIRV_AnyPtr, SPIRV_AnyArray, SPIRV_AnyRTArray, SPIRV_AnyStruct,
-     SPIRV_AnyCooperativeMatrix, SPIRV_AnyJointMatrix, SPIRV_AnyMatrix,
-     SPIRV_AnySampledImage
-@@ -4764,6 +4787,12 @@ def SPIRV_FPFMM_AllowReassocINTEL : I32BitEnumAttrCaseBit<"AllowReassocINTEL", 1
-   ];
- }
-
+     SPIRV_AnyCooperativeMatrix, SPIRV_AnyMatrix, SPIRV_AnySampledImage
+   ]>;
+@@ -4745,4 +4770,10 @@ def SPIRV_FPFastMathModeAttr :
+       SPIRV_FPFMM_AllowReassocINTEL
+     ]>;
+ 
 +def SPIRV_FPE_BFloat16KHR     :  I32EnumAttrCase<"BFloat16KHR", 0>;
 +def SPIRV_FP_Encoding  :
 +     SPIRV_I32EnumAttr<"FPEncoding", "Valid floating-point encoding", "fpEncoding", [
 +     SPIRV_FPE_BFloat16KHR
 +     ]>;
 +
- def SPIRV_FPFastMathModeAttr :
-     SPIRV_BitEnumAttr<"FPFastMathMode", "Indicates a floating-point fast math flag", "fastmath_mode", [
-       SPIRV_FPFMM_None, SPIRV_FPFMM_NotNaN, SPIRV_FPFMM_NotInf, SPIRV_FPFMM_NSZ,
+ #endif // MLIR_DIALECT_SPIRV_IR_BASE
 diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
 index b5ca27d7d753..703920e42c60 100644
 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td

lib/Conversion/XeTileToXeGPU/ArithOpConversion.cpp

@@ -311,8 +311,7 @@ class SgVectorMultiDimReductionOpPattern
 
     rewriter.setInsertionPoint(op);
     // doing reduction on outer dimension
-    if (mlir::isConstantIntValue(dims[0], 0) &&
-        mlir::isConstantIntValue(dims[1], 2)) {
+    if (dims[0] == 0 && dims[1] == 2) {
       auto intermediates = lowerOuterReduction(sources, shape, op.getKind(),
                                                loc, elemTy, rewriter);
       {
@@ -330,8 +329,7 @@ class SgVectorMultiDimReductionOpPattern
     }
 
     // doing reduction on inner dimension
-    if (mlir::isConstantIntValue(dims[0], 1) &&
-        mlir::isConstantIntValue(dims[1], 3)) {
+    if (dims[0] == 1 && dims[1] == 3) {
       auto intermediates = lowerInnerReductionWithIntraVectorShuffles(
           sources, shape, op.getKind(), loc, elemTy, rewriter);
 

lib/Dialect/XeTile/Transforms/Blocking.cpp

@@ -458,8 +458,8 @@ struct VectorMultiDimReductionOpPattern
     // will be transformed to
     // multi_reduction<add>, %e, %a[1, 3]: vector<16x2x1x16xf16> to
     // vector<16x1xf16>
-    auto dim = mlir::cast<mlir::IntegerAttr>(reductionDims[0]).getInt();
-    auto newReductionDims = rewriter.getI64ArrayAttr({dim, dim + 2});
+    auto dim = reductionDims[0];
+    auto newReductionDims = rewriter.getDenseI64ArrayAttr({dim, dim + 2});
 
     auto newDestShape =
         (dim == 0)

lib/Dialect/XeTile/Transforms/Canonicalization.cpp

@@ -278,14 +278,12 @@ struct VectorMultiReductionToXeTileReduce
       return mlir::failure();
     // If result is not 1D, we can not convert it to xetile.reduce. This
     // requires that the reduction dimensions has rank 1.
-    auto reductionDims = op.getReductionDims().getValue();
+    auto reductionDims = op.getReductionDims();
     if (reductionDims.size() != 1)
       return mlir::failure();
 
     // Create an equivalent XeTileReduceOp
-    int64_t reduceDim = llvm::cast<mlir::IntegerAttr>(reductionDims[0])
-                            .getValue()
-                            .getSExtValue();
+    int64_t reduceDim = reductionDims[0];
     auto resultTy = llvm::cast<mlir::VectorType>(op.getType());
     auto xetileResultTy = mlir::VectorType::get(
         (reduceDim == 0 ? llvm::ArrayRef<int64_t>({1, resultTy.getDimSize(0)})

lib/Transforms/PropagatePackedLayout.cpp

@@ -160,7 +160,7 @@ class LayoutAnalysisImpl
 public:
   using SparseBackwardDataFlowAnalysis::SparseBackwardDataFlowAnalysis;
 
-  void visitOperation(mlir::Operation *op,
+  mlir::LogicalResult visitOperation(mlir::Operation *op,
                       mlir::ArrayRef<LayoutLattice *> operands,
                       mlir::ArrayRef<const LayoutLattice *> results) override {
     if (mlir::OpTrait::hasElementwiseMappableTraits(op)) {
@@ -182,7 +182,7 @@ class LayoutAnalysisImpl
         propagateIfChanged(argLattice, argLattice->meet(tmpLayout));
       }
 
-      return;
+      return mlir::success();
     }
 
     if (auto dpas = mlir::dyn_cast<mlir::xegpu::DpasOp>(op)) {
@@ -193,12 +193,13 @@ class LayoutAnalysisImpl
           propagateIfChanged(operand, operand->meet(std::nullopt));
         }
       }
-      return;
+      return mlir::success();
     }
 
     // Unknown ops: mark all args as invalid layout (no layout change).
     for (auto operand : operands)
       propagateIfChanged(operand, operand->meet(std::nullopt));
+    return mlir::success();
   }
 
   void visitBranchOperand(mlir::OpOperand &operand) override {}

lib/Transforms/VnniTransformation.cpp

@@ -127,7 +127,7 @@ class LayoutAnalysisImpl
 public:
   using SparseBackwardDataFlowAnalysis::SparseBackwardDataFlowAnalysis;
 
-  void visitOperation(mlir::Operation *op,
+  mlir::LogicalResult visitOperation(mlir::Operation *op,
                       mlir::ArrayRef<LayoutLattice *> operands,
                       mlir::ArrayRef<const LayoutLattice *> results) override {
     // the B operand of a dpas operation is always in vnni layout
@@ -144,7 +144,7 @@ class LayoutAnalysisImpl
         // for C operand, it cannot be in vnni format
         propagateIfChanged(operands[2], operands[2]->meet(Layout(false)));
       }
-      return;
+      return mlir::success();
     }
 
     if (mlir::OpTrait::hasElementwiseMappableTraits(op)) {
@@ -175,7 +175,7 @@ class LayoutAnalysisImpl
         for (auto &&lattice : operands)
           propagateIfChanged(lattice, lattice->meet(layout));
       }
-      return;
+      return mlir::success();
     }
 
     if (auto extractStrideSliceOp =
@@ -186,7 +186,7 @@ class LayoutAnalysisImpl
         layout = Layout::meet(layout, Layout(isVNNIApplicable(srcTy)));
         propagateIfChanged(operands[0], operands[0]->meet(layout));
       }
-      return;
+      return mlir::success();
     }
 
     if (auto extractOp = mlir::dyn_cast<mlir::vector::ExtractOp>(op)) {
@@ -201,12 +201,13 @@ class LayoutAnalysisImpl
         layout = Layout::meet(layout, Layout(isVNNIApplicable(vecTy)));
         propagateIfChanged(operands[0], operands[0]->meet(layout));
       }
-      return;
+      return mlir::success();
     }
 
     // Unknown ops: mark all args as non-vnni layout (no layout change).
     for (auto operand : operands)
       propagateIfChanged(operand, operand->join(Layout(false)));
+    return mlir::success();
   }
 
   void visitBranchOperand(mlir::OpOperand &operand) override {}