From acfe8373ba636e2ae8a287b7168a3fbf6a447d6b Mon Sep 17 00:00:00 2001 From: Garra1980 Date: Thu, 21 Aug 2025 00:13:27 +0200 Subject: [PATCH 1/2] [LLVM Pulldown] Bump LLVM rev b44e47a68f9b49a6283b1beaab3af55fa39e8907 --- build_tools/llvm_version.txt | 2 +- ...downstream-defintion-changes-and-vec.patch | 61 +++++++++++-------- 2 files changed, 37 insertions(+), 26 deletions(-) diff --git a/build_tools/llvm_version.txt b/build_tools/llvm_version.txt index 87f326522..6e7511183 100644 --- a/build_tools/llvm_version.txt +++ b/build_tools/llvm_version.txt @@ -1 +1 @@ -20a829937cc8cd69170b75c0bb7f31ad9ba19677 +b44e47a68f9b49a6283b1beaab3af55fa39e8907 \ No newline at end of file diff --git a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch index d27bb5229..e57999777 100644 --- a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch +++ b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch @@ -1,19 +1,19 @@ -From e689c226f0d1cfc3353225e2c9f0c45d307fd960 Mon Sep 17 00:00:00 2001 +From 6a3b9a4936f774957b6a1cedcae40a355fb9670e Mon Sep 17 00:00:00 2001 From: Garra1980 -Date: Tue, 5 Aug 2025 23:19:34 +0200 +Date: Wed, 20 Aug 2025 01:20:08 +0200 Subject: [PATCH] xegpu temporary downstream defintion changes and vec --- - mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 6 ++++++ - mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp | 7 ++++++- - mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp | 7 ++++--- - 3 files changed, 16 insertions(+), 4 deletions(-) + mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 5 +++++ + mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp | 7 ++++++- + mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp | 10 ++++++---- + 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td -index 7f4d4f1381df..ebd4f1a3f66a 100644 +index eb54d6887681..b849c6b97d9d 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td -@@ -373,6 +373,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [ +@@ -329,6 +329,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [ OptionalAttr: $const_offsets, OptionalAttr: $packed, OptionalAttr: $transpose, @@ -21,21 +21,21 @@ index 7f4d4f1381df..ebd4f1a3f66a 100644 OptionalAttr: $l1_hint, OptionalAttr: $l2_hint, OptionalAttr: $l3_hint); -@@ -1147,4 +1148,9 @@ def XeGPU_ConvertLayoutOp: XeGPU_Op<"convert_layout", [Pure, AllTypesMatch<["sou - let hasCanonicalizer = 1; +@@ -1260,5 +1261,9 @@ def XeGPU_MemDescSubviewOp: XeGPU_Op<"mem_desc_subview", + let hasVerifier = 1; } - + +def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> { + let summary = "prevents the compiler from scheduling."; + let assemblyFormat = [{ attr-dict }]; +} -+ + #endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD diff --git a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp -index 80107554144c..4050a12f2eb8 100644 +index 819c2e5973ff..545f1d77156c 100644 --- a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp +++ b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp -@@ -201,7 +201,9 @@ struct TransferReadLowering : public OpRewritePattern { +@@ -485,7 +485,9 @@ struct TransferReadLowering : public OpRewritePattern { // By default, no specific caching policy is assigned. xegpu::CachePolicyAttr hint = nullptr; auto loadOp = xegpu::LoadNdOp::create(rewriter, loc, vecTy, ndDesc, @@ -45,7 +45,7 @@ index 80107554144c..4050a12f2eb8 100644 /*l1_hint=*/hint, /*l2_hint=*/hint, /*l3_hint=*/hint); rewriter.replaceOp(readOp, loadOp); -@@ -270,7 +272,10 @@ struct LoadLowering : public OpRewritePattern { +@@ -569,7 +571,10 @@ struct LoadLowering : public OpRewritePattern { // By default, no specific caching policy is assigned. xegpu::CachePolicyAttr hint = nullptr; auto loadNdOp = xegpu::LoadNdOp::create( @@ -58,36 +58,47 @@ index 80107554144c..4050a12f2eb8 100644 /*l2_hint=*/hint, /*l3_hint=*/hint); rewriter.replaceOp(loadOp, loadNdOp); diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp -index 33450f3fa229..528b9d55ee61 100644 +index 906c71d8b8da..ecee53c56a54 100644 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp -@@ -65,6 +65,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) { +@@ -78,6 +78,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) { return true; auto kind = attr.getValue(); return kind == CachePolicy::CACHED || kind == CachePolicy::UNCACHED || + kind == CachePolicy::STREAMING || kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH; } - -@@ -419,8 +420,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, + +@@ -438,8 +439,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, xegpu::CachePolicyAttr l3_hint) { - + return build(builder, state, retType, tensorDesc, ValueRange(), - DenseI64ArrayAttr(), packed, transpose, l1_hint, l2_hint, - l3_hint); -+ DenseI64ArrayAttr(), packed, transpose, nullptr, ++ DenseI64ArrayAttr(), packed, transpose, nullptr, /*transpose_bit_width*/ + l1_hint, l2_hint, l3_hint); } - + + void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, +@@ -455,7 +456,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, + auto staticOffsetsAttr = builder.getDenseI64ArrayAttr(staticOffsets); + + build(builder, state, retType, tensorDesc, dynamicOffsets, staticOffsetsAttr, +- packed, transpose, l1_hint, l2_hint, l3_hint); ++ packed, transpose, nullptr, /*transpose_bit_width*/ ++ l1_hint, l2_hint, l3_hint); + } + LogicalResult LoadNdOp::verify() { -@@ -482,7 +483,7 @@ LogicalResult LoadNdOp::verify() { +@@ -517,7 +519,7 @@ LogicalResult LoadNdOp::verify() { mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored."; } - + - if (getPacked()) { + if (getPacked() || getTransposeBitWidth() == 32) { if (tdescTy.getRank() == 2) { const int axis = 0; auto vnni_factor = valueShape.back(); --- +-- 2.34.1 + From d6e75f9f8483fc3c575bae5e6879cf1589af5d57 Mon Sep 17 00:00:00 2001 From: Garra1980 Date: Thu, 21 Aug 2025 00:14:10 +0200 Subject: [PATCH 2/2] fix pre-commit --- build_tools/llvm_version.txt | 2 +- ...downstream-defintion-changes-and-vec.patch | 19 +++++++++---------- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/build_tools/llvm_version.txt b/build_tools/llvm_version.txt index 6e7511183..55d3649ae 100644 --- a/build_tools/llvm_version.txt +++ b/build_tools/llvm_version.txt @@ -1 +1 @@ -b44e47a68f9b49a6283b1beaab3af55fa39e8907 \ No newline at end of file +b44e47a68f9b49a6283b1beaab3af55fa39e8907 diff --git a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch index e57999777..50ac7dd47 100644 --- a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch +++ b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch @@ -24,12 +24,12 @@ index eb54d6887681..b849c6b97d9d 100644 @@ -1260,5 +1261,9 @@ def XeGPU_MemDescSubviewOp: XeGPU_Op<"mem_desc_subview", let hasVerifier = 1; } - + +def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> { + let summary = "prevents the compiler from scheduling."; + let assemblyFormat = [{ attr-dict }]; +} - + #endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD diff --git a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp index 819c2e5973ff..545f1d77156c 100644 @@ -68,37 +68,36 @@ index 906c71d8b8da..ecee53c56a54 100644 + kind == CachePolicy::STREAMING || kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH; } - + @@ -438,8 +439,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, xegpu::CachePolicyAttr l3_hint) { - + return build(builder, state, retType, tensorDesc, ValueRange(), - DenseI64ArrayAttr(), packed, transpose, l1_hint, l2_hint, - l3_hint); + DenseI64ArrayAttr(), packed, transpose, nullptr, /*transpose_bit_width*/ + l1_hint, l2_hint, l3_hint); } - + void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, @@ -455,7 +456,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType, auto staticOffsetsAttr = builder.getDenseI64ArrayAttr(staticOffsets); - + build(builder, state, retType, tensorDesc, dynamicOffsets, staticOffsetsAttr, - packed, transpose, l1_hint, l2_hint, l3_hint); + packed, transpose, nullptr, /*transpose_bit_width*/ + l1_hint, l2_hint, l3_hint); } - + LogicalResult LoadNdOp::verify() { @@ -517,7 +519,7 @@ LogicalResult LoadNdOp::verify() { mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored."; } - + - if (getPacked()) { + if (getPacked() || getTransposeBitWidth() == 32) { if (tdescTy.getRank() == 2) { const int axis = 0; auto vnni_factor = valueShape.back(); --- +-- 2.34.1 -