@@ -1177,50 +1177,52 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
11771177bool get_cpu_bus (uint32 msmDomain, uint32 msmBus, uint32 msmDev, uint32 msmFunc, uint32 &cpuBusValid, std::vector<uint32> &cpuBusNo, int &cpuPackageId)
11781178{
11791179 // std::cout << "get_cpu_bus: d=" << std::hex << msmDomain << ",b=" << msmBus << ",d=" << msmDev << ",f=" << msmFunc << std::dec << " \n";
1180- try {
1181- PciHandleType h (msmDomain, msmBus, msmDev, msmFunc);
1180+ try
1181+ {
1182+ PciHandleType h (msmDomain, msmBus, msmDev, msmFunc);
11821183
1183- h.read32 (SPR_MSM_REG_CPUBUSNO_VALID_OFFSET, &cpuBusValid);
1184- if (cpuBusValid == (std::numeric_limits<uint32>::max)()) {
1185- std::cerr << " Failed to read CPUBUSNO_VALID" << std::endl;
1186- return false ;
1187- }
1184+ h.read32 (SPR_MSM_REG_CPUBUSNO_VALID_OFFSET, &cpuBusValid);
1185+ if (cpuBusValid == (std::numeric_limits<uint32>::max)()) {
1186+ std::cerr << " Failed to read CPUBUSNO_VALID" << std::endl;
1187+ return false ;
1188+ }
11881189
1189- cpuBusNo.resize (8 );
1190- for (int i = 0 ; i < 4 ; ++i)
1191- {
1192- h.read32 (SPR_MSM_REG_CPUBUSNO0_OFFSET + i * 4 , &cpuBusNo[i]);
1190+ cpuBusNo.resize (8 );
1191+ for (int i = 0 ; i < 4 ; ++i)
1192+ {
1193+ h.read32 (SPR_MSM_REG_CPUBUSNO0_OFFSET + i * 4 , &cpuBusNo[i]);
11931194
1194- h.read32 (SPR_MSM_REG_CPUBUSNO4_OFFSET + i * 4 , &cpuBusNo[i + 4 ]);
1195+ h.read32 (SPR_MSM_REG_CPUBUSNO4_OFFSET + i * 4 , &cpuBusNo[i + 4 ]);
11951196
1196- if (cpuBusNo[i] == (std::numeric_limits<uint32>::max)() ||
1197- cpuBusNo[i + 4 ] == (std::numeric_limits<uint32>::max)())
1197+ if (cpuBusNo[i] == (std::numeric_limits<uint32>::max)() ||
1198+ cpuBusNo[i + 4 ] == (std::numeric_limits<uint32>::max)())
1199+ {
1200+ std::cerr << " Failed to read CPUBUSNO registers" << std::endl;
1201+ return false ;
1202+ }
1203+ }
1204+
1205+ /*
1206+ * It's possible to have not enabled first stack that's why
1207+ * need to find the first valid bus to read CSR
1208+ */
1209+ int firstValidBusId = 0 ;
1210+ while (!((cpuBusValid >> firstValidBusId) & 0x1 )) firstValidBusId++;
1211+ int cpuBusNo0 = (cpuBusNo[(int )(firstValidBusId / 4 )] >> ((firstValidBusId % 4 ) * 8 )) & 0xff ;
1212+
1213+ uint32 sadControlCfg = 0x0 ;
1214+ PciHandleType sad_cfg_handler (msmDomain, cpuBusNo0, 0 , 0 );
1215+ sad_cfg_handler.read32 (SPR_SAD_REG_CTL_CFG_OFFSET, &sadControlCfg);
1216+ if (sadControlCfg == (std::numeric_limits<uint32>::max)())
11981217 {
1199- std::cerr << " Failed to read CPUBUSNO registers " << std::endl;
1218+ std::cerr << " Failed to read SAD_CONTROL_CFG " << std::endl;
12001219 return false ;
12011220 }
1202- }
1221+ cpuPackageId = sadControlCfg & 0xf ;
12031222
1204- /*
1205- * It's possible to have not enabled first stack that's why
1206- * need to find the first valid bus to read CSR
1207- */
1208- int firstValidBusId = 0 ;
1209- while (!((cpuBusValid >> firstValidBusId) & 0x1 )) firstValidBusId++;
1210- int cpuBusNo0 = (cpuBusNo[(int )(firstValidBusId / 4 )] >> ((firstValidBusId % 4 ) * 8 )) & 0xff ;
1211-
1212- uint32 sadControlCfg = 0x0 ;
1213- PciHandleType sad_cfg_handler (msmDomain, cpuBusNo0, 0 , 0 );
1214- sad_cfg_handler.read32 (SPR_SAD_REG_CTL_CFG_OFFSET, &sadControlCfg);
1215- if (sadControlCfg == (std::numeric_limits<uint32>::max)())
1216- {
1217- std::cerr << " Failed to read SAD_CONTROL_CFG" << std::endl;
1218- return false ;
1223+ return true ;
12191224 }
1220- cpuPackageId = sadControlCfg & 0xf ;
1221-
1222- return true ;
1223- } catch (...)
1225+ catch (...)
12241226 {
12251227 std::cerr << " Warning: unable to enumerate CPU Buses" << std::endl;
12261228 return false ;
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