@@ -1177,50 +1177,52 @@ int load_events(const std::string &fn, std::map<std::string, uint32_t> &ofm,
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bool get_cpu_bus (uint32 msmDomain, uint32 msmBus, uint32 msmDev, uint32 msmFunc, uint32 &cpuBusValid, std::vector<uint32> &cpuBusNo, int &cpuPackageId)
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{
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// std::cout << "get_cpu_bus: d=" << std::hex << msmDomain << ",b=" << msmBus << ",d=" << msmDev << ",f=" << msmFunc << std::dec << " \n";
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- try {
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- PciHandleType h (msmDomain, msmBus, msmDev, msmFunc);
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+ try
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+ {
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+ PciHandleType h (msmDomain, msmBus, msmDev, msmFunc);
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- h.read32 (SPR_MSM_REG_CPUBUSNO_VALID_OFFSET, &cpuBusValid);
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- if (cpuBusValid == (std::numeric_limits<uint32>::max)()) {
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- std::cerr << " Failed to read CPUBUSNO_VALID" << std::endl;
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- return false ;
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- }
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+ h.read32 (SPR_MSM_REG_CPUBUSNO_VALID_OFFSET, &cpuBusValid);
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+ if (cpuBusValid == (std::numeric_limits<uint32>::max)()) {
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+ std::cerr << " Failed to read CPUBUSNO_VALID" << std::endl;
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+ return false ;
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+ }
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- cpuBusNo.resize (8 );
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- for (int i = 0 ; i < 4 ; ++i)
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- {
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- h.read32 (SPR_MSM_REG_CPUBUSNO0_OFFSET + i * 4 , &cpuBusNo[i]);
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+ cpuBusNo.resize (8 );
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+ for (int i = 0 ; i < 4 ; ++i)
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+ {
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+ h.read32 (SPR_MSM_REG_CPUBUSNO0_OFFSET + i * 4 , &cpuBusNo[i]);
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- h.read32 (SPR_MSM_REG_CPUBUSNO4_OFFSET + i * 4 , &cpuBusNo[i + 4 ]);
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+ h.read32 (SPR_MSM_REG_CPUBUSNO4_OFFSET + i * 4 , &cpuBusNo[i + 4 ]);
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- if (cpuBusNo[i] == (std::numeric_limits<uint32>::max)() ||
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- cpuBusNo[i + 4 ] == (std::numeric_limits<uint32>::max)())
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+ if (cpuBusNo[i] == (std::numeric_limits<uint32>::max)() ||
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+ cpuBusNo[i + 4 ] == (std::numeric_limits<uint32>::max)())
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+ {
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+ std::cerr << " Failed to read CPUBUSNO registers" << std::endl;
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+ return false ;
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+ }
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+ }
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+
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+ /*
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+ * It's possible to have not enabled first stack that's why
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+ * need to find the first valid bus to read CSR
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+ */
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+ int firstValidBusId = 0 ;
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+ while (!((cpuBusValid >> firstValidBusId) & 0x1 )) firstValidBusId++;
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+ int cpuBusNo0 = (cpuBusNo[(int )(firstValidBusId / 4 )] >> ((firstValidBusId % 4 ) * 8 )) & 0xff ;
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+
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+ uint32 sadControlCfg = 0x0 ;
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+ PciHandleType sad_cfg_handler (msmDomain, cpuBusNo0, 0 , 0 );
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+ sad_cfg_handler.read32 (SPR_SAD_REG_CTL_CFG_OFFSET, &sadControlCfg);
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+ if (sadControlCfg == (std::numeric_limits<uint32>::max)())
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{
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- std::cerr << " Failed to read CPUBUSNO registers " << std::endl;
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+ std::cerr << " Failed to read SAD_CONTROL_CFG " << std::endl;
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return false ;
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}
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- }
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+ cpuPackageId = sadControlCfg & 0xf ;
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- /*
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- * It's possible to have not enabled first stack that's why
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- * need to find the first valid bus to read CSR
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- */
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- int firstValidBusId = 0 ;
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- while (!((cpuBusValid >> firstValidBusId) & 0x1 )) firstValidBusId++;
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- int cpuBusNo0 = (cpuBusNo[(int )(firstValidBusId / 4 )] >> ((firstValidBusId % 4 ) * 8 )) & 0xff ;
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-
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- uint32 sadControlCfg = 0x0 ;
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- PciHandleType sad_cfg_handler (msmDomain, cpuBusNo0, 0 , 0 );
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- sad_cfg_handler.read32 (SPR_SAD_REG_CTL_CFG_OFFSET, &sadControlCfg);
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- if (sadControlCfg == (std::numeric_limits<uint32>::max)())
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- {
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- std::cerr << " Failed to read SAD_CONTROL_CFG" << std::endl;
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- return false ;
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+ return true ;
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}
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- cpuPackageId = sadControlCfg & 0xf ;
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-
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- return true ;
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- } catch (...)
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+ catch (...)
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{
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std::cerr << " Warning: unable to enumerate CPU Buses" << std::endl;
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return false ;
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