rename extract_bits_ui into extract_bits_32

to reduce risk of cutting bits of wider input integers

Change-Id: Iaac12ef1147c9d292cf7f6a5d7a32a20e81b40b5

Author: rdementi

src/cpucounters.cpp

@@ -253,13 +253,13 @@ void PCM::readCoreCounterConfig(const bool complainAboutMSR)
         // get counter related info
         PCM_CPUID_INFO cpuinfo;
         pcm_cpuid(0xa, cpuinfo);
-        perfmon_version = extract_bits_ui(cpuinfo.array[0], 0, 7);
-        core_gen_counter_num_max = extract_bits_ui(cpuinfo.array[0], 8, 15);
-        core_gen_counter_width = extract_bits_ui(cpuinfo.array[0], 16, 23);
+        perfmon_version = extract_bits_32(cpuinfo.array[0], 0, 7);
+        core_gen_counter_num_max = extract_bits_32(cpuinfo.array[0], 8, 15);
+        core_gen_counter_width = extract_bits_32(cpuinfo.array[0], 16, 23);
         if (perfmon_version > 1)
         {
-            core_fixed_counter_num_max = extract_bits_ui(cpuinfo.array[3], 0, 4);
-            core_fixed_counter_width = extract_bits_ui(cpuinfo.array[3], 5, 12);
+            core_fixed_counter_num_max = extract_bits_32(cpuinfo.array[3], 0, 4);
+            core_fixed_counter_width = extract_bits_32(cpuinfo.array[3], 5, 12);
         }
         else if (1 == perfmon_version)
         {
@@ -321,7 +321,7 @@ bool PCM::isFixedCounterSupported(unsigned c)
     {
         PCM_CPUID_INFO cpuinfo;
         pcm_cpuid(0xa, cpuinfo);
-        return extract_bits_ui(cpuinfo.reg.ecx, c, c) || (extract_bits_ui(cpuinfo.reg.edx, 4, 0) > c);
+        return extract_bits_32(cpuinfo.reg.ecx, c, c) || (extract_bits_32(cpuinfo.reg.edx, 4, 0) > c);
     }
     return false;
 }
@@ -340,7 +340,7 @@ bool PCM::isHWTMAL1Supported() const
         supported = 0;
         PCM_CPUID_INFO cpuinfo;
         pcm_cpuid(1, cpuinfo);
-        if (extract_bits_ui(cpuinfo.reg.ecx, 15, 15) && MSR.size())
+        if (extract_bits_32(cpuinfo.reg.ecx, 15, 15) && MSR.size())
         {
             uint64 perf_cap;
             if (MSR[0]->read(MSR_PERF_CAPABILITIES, &perf_cap) == sizeof(uint64))
@@ -1125,12 +1125,12 @@ bool PCM::discoverSystemTopology()
             {
                 pcm_cpuid(0x1F, subleaf, cpuid_args);
                 domain d;
-                d.type = (TopologyEntry::DomainTypeID)extract_bits_ui(cpuid_args.reg.ecx, 8, 15);
+                d.type = (TopologyEntry::DomainTypeID)extract_bits_32(cpuid_args.reg.ecx, 8, 15);
                 if (d.type == TopologyEntry::DomainTypeID::InvalidDomainTypeID)
                 {
                     break;
                 }
-                d.nextLevelShift = extract_bits_ui(cpuid_args.reg.eax, 0, 4);
+                d.nextLevelShift = extract_bits_32(cpuid_args.reg.eax, 0, 4);
                 d.levelShift = topologyDomains.empty() ? 0 : topologyDomains.back().nextLevelShift;
                 d.width = d.nextLevelShift - d.levelShift;
                 topologyDomains.push_back(d);
@@ -1182,11 +1182,11 @@ bool PCM::discoverSystemTopology()
                 if (di != topologyDomainMap.end())
                 {
                     const auto & d = di->second;
-                    return extract_bits_ui(apic_id, d.levelShift, d.nextLevelShift - 1);
+                    return extract_bits_32(apic_id, d.levelShift, d.nextLevelShift - 1);
                 }
                 return 0U;
             };
-            entry.tile_id = extract_bits_ui(getAPICID(0xb), l2CacheMaskShift, 31);
+            entry.tile_id = extract_bits_32(getAPICID(0xb), l2CacheMaskShift, 31);
             const int apic_id = getAPICID(0x1F);
             entry.thread_id = getID(apic_id, TopologyEntry::DomainTypeID::LogicalProcessorDomain);
             entry.core_id = getID(apic_id, TopologyEntry::DomainTypeID::CoreDomain);
@@ -1210,7 +1210,7 @@ bool PCM::discoverSystemTopology()
             };
             domain d1 = getDomain( TopologyEntry::DomainTypeID::CoreDomain );
             domain d2 = getDomain( TopologyEntry::DomainTypeID::SocketPackageDomain );
-            entry.socket_unique_core_id = extract_bits_ui( apic_id, d1.levelShift, d2.levelShift - 1 );
+            entry.socket_unique_core_id = extract_bits_32( apic_id, d1.levelShift, d2.levelShift - 1 );
         }
         else
         {
@@ -1233,8 +1233,8 @@ bool PCM::discoverSystemTopology()
         (void)core;
         return false;
 #endif
-        entry.native_cpu_model = extract_bits_ui(cpuid_args.reg.eax, 0, 23);
-        entry.core_type = (TopologyEntry::CoreType) extract_bits_ui(cpuid_args.reg.eax, 24, 31);
+        entry.native_cpu_model = extract_bits_32(cpuid_args.reg.eax, 0, 23);
+        entry.core_type = (TopologyEntry::CoreType) extract_bits_32(cpuid_args.reg.eax, 24, 31);
         return true;
     };
 
@@ -1654,7 +1654,7 @@ bool PCM::detectNominalFrequency()
         {
             PCM_CPUID_INFO cpuinfo;
             pcm_cpuid(0x16, cpuinfo);
-            nominal_frequency = uint64(extract_bits_ui(cpuinfo.reg.eax, 0, 15)) * 1000000ULL;;
+            nominal_frequency = uint64(extract_bits_32(cpuinfo.reg.eax, 0, 15)) * 1000000ULL;;
         }
         if (!nominal_frequency)
         {
@@ -6224,7 +6224,7 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile
                                             const auto pcicfgOffset = extract_bits(membarBits, 0, 15);
                                             uint32 memBarOffset = 0;
                                             pciHandle.read32(pcicfgOffset, &memBarOffset);
-                                            return size_t(extract_bits_ui(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos;
+                                            return size_t(extract_bits_32(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos;
                                         }
                                         return 0;
                                     };
@@ -6686,7 +6686,7 @@ void PCM::readPCICFGRegisters(SystemCounterState& systemState)
                 {
                 case 16:
                     h->read32(offset, &value32);
-                    value = (uint64)extract_bits_ui(value32, 0, 15);
+                    value = (uint64)extract_bits_32(value32, 0, 15);
                     break;
                 case 32:
                     h->read32(offset, &value32);
@@ -6756,7 +6756,7 @@ void PCM::readMMIORegisters(SystemCounterState& systemState)
                 {
                 case 16:
                     value32 = h->read32(offset);
-                    value = (uint64)extract_bits_ui(value32, 0, 15);
+                    value = (uint64)extract_bits_32(value32, 0, 15);
                     break;
                 case 32:
                     value32 = h->read32(offset);
@@ -9867,7 +9867,7 @@ uint64 ServerUncorePMUs::computeQPISpeed(const uint32 core_nr, const int cpufami
                uint32 value = 0;
                if (reg.read32(UPI_SPEED_REGISTER_OFFSET, &value) == sizeof(uint32))
                {
-                   const size_t speedMT = UPISpeedMap[extract_bits_ui(value, regBits.first, regBits.second)];
+                   const size_t speedMT = UPISpeedMap[extract_bits_32(value, regBits.first, regBits.second)];
                    if (false)
                    {
                        std::cerr << "speedMT: " << speedMT << "\n";
@@ -10575,11 +10575,11 @@ void PCM::programIDXAccelCounters(uint32 accel, std::vector<uint64_t> &events, s
                 *ctrl_reg = 0x0;
             }
 
-            *filter_wq_reg = extract_bits_ui(filters_wq.at(i), 0, 15);            
-            *filter_eng_reg = extract_bits_ui(filters_eng.at(i), 0, 15);
-            *filter_tc_reg = extract_bits_ui(filters_tc.at(i), 0, 7);
-            *filter_pgsz_reg = extract_bits_ui(filters_pgsz.at(i), 0, 7);
-            *filter_xfersz_reg = extract_bits_ui(filters_xfersz.at(i), 0, 7);
+            *filter_wq_reg = extract_bits_32(filters_wq.at(i), 0, 15);            
+            *filter_eng_reg = extract_bits_32(filters_eng.at(i), 0, 15);
+            *filter_tc_reg = extract_bits_32(filters_tc.at(i), 0, 7);
+            *filter_pgsz_reg = extract_bits_32(filters_pgsz.at(i), 0, 7);
+            *filter_xfersz_reg = extract_bits_32(filters_xfersz.at(i), 0, 7);
 
             if (pmu.getPERFMode() == false)
             {

src/pcm-lspci.cpp

@@ -124,8 +124,8 @@ int mainThrows(int /*argc*/, char * /*argv*/[])
                     PciHandleType h(0, bus, device, function);
                     uint32 value = 0;
                     h.read32(0, &value);
-                    const uint32 vendor = extract_bits_ui(value, 0, 15);
-                    const uint32 deviceID = extract_bits_ui(value, 16, 31);
+                    const uint32 vendor = extract_bits_32(value, 0, 15);
+                    const uint32 deviceID = extract_bits_32(value, 16, 31);
                     std::cout << "0:" << bus << ":" << device << ":" << function << " vendor 0x" << std::hex << vendor << " device 0x" << deviceID << std::dec << "\n";
                 }
             }

src/topologyentry.h

@@ -96,10 +96,10 @@ struct PCM_API TopologyEntry // describes a core
 
 inline void fillEntry(TopologyEntry & entry, const uint32 & smtMaskWidth, const uint32 & coreMaskWidth, const uint32 & l2CacheMaskShift, const int apic_id)
 {
-    entry.thread_id = smtMaskWidth ? extract_bits_ui(apic_id, 0, smtMaskWidth - 1) : 0;
-    entry.core_id = (smtMaskWidth + coreMaskWidth) ? extract_bits_ui(apic_id, smtMaskWidth, smtMaskWidth + coreMaskWidth - 1) : 0;
-    entry.socket_id = extract_bits_ui(apic_id, smtMaskWidth + coreMaskWidth, 31);
-    entry.tile_id = extract_bits_ui(apic_id, l2CacheMaskShift, 31);
+    entry.thread_id = smtMaskWidth ? extract_bits_32(apic_id, 0, smtMaskWidth - 1) : 0;
+    entry.core_id = (smtMaskWidth + coreMaskWidth) ? extract_bits_32(apic_id, smtMaskWidth, smtMaskWidth + coreMaskWidth - 1) : 0;
+    entry.socket_id = extract_bits_32(apic_id, smtMaskWidth + coreMaskWidth, 31);
+    entry.tile_id = extract_bits_32(apic_id, l2CacheMaskShift, 31);
     entry.socket_unique_core_id = entry.core_id;
 }
 
@@ -121,8 +121,8 @@ inline bool initCoreMasks(uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32
             { // if EBX ==0 then this subleaf is not valid, we can exit the loop
                 break;
             }
-            levelType = extract_bits_ui(cpuid_args.array[2], 8, 15);
-            levelShift = extract_bits_ui(cpuid_args.array[0], 0, 4);
+            levelType = extract_bits_32(cpuid_args.array[2], 8, 15);
+            levelShift = extract_bits_32(cpuid_args.array[0], 0, 4);
             switch (levelType)
             {
             case 1: //level type is SMT, so levelShift is the SMT_Mask_Width
@@ -160,7 +160,7 @@ inline bool initCoreMasks(uint32 & smtMaskWidth, uint32 & coreMaskWidth, uint32
         uint32 l2CacheMaskWidth;
 
         pcm_cpuid(0x4, 2, cpuid_args); // get ID for L2 cache
-        l2CacheMaskWidth = 1 + extract_bits_ui(cpuid_args.array[0],14,25); // number of APIC IDs sharing L2 cache
+        l2CacheMaskWidth = 1 + extract_bits_32(cpuid_args.array[0],14,25); // number of APIC IDs sharing L2 cache
     #ifdef PCM_DEBUG_TOPOLOGY
         threadsSharingL2 = l2CacheMaskWidth;
     #endif

src/types.h

@@ -1581,7 +1581,7 @@ inline uint32 build_bit_ui(uint32 beg, uint32 end)
     return myll;
 }
 
-inline uint32 extract_bits_ui(uint32 myin, uint32 beg, uint32 end)
+inline uint32 extract_bits_32(uint32 myin, uint32 beg, uint32 end)
 {
     uint32 myll = 0;
     uint32 beg1, end1;