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add doc/PCM_IIO_README.md
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README.md

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@@ -42,7 +42,7 @@ PCM provides a number of command-line utilities for real-time monitoring:
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- **pcm-latency** : monitor L1 cache miss and DDR/PMM memory latency
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- **pcm-pcie** : monitor PCIe bandwidth per-socket
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- **pcm-iio** : monitor PCIe bandwidth per PCIe device
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- **pcm-iio** : [monitor PCIe bandwidth per PCIe bus/device](doc/PCM_IIO_README.md)
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![pcm-iio output](https://raw.githubusercontent.com/wiki/intel/pcm/pcm-iio.png)
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- **pcm-numa** : monitor local and remote memory accesses

doc/PCM_IIO_README.md

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## Purpose:
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PCM-IIO tool monitors PCIe transactions with a breakdown per PCIe bus (IIO stack) and/or PCIe devices.
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## Tool UI introduction:
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Inbound (PCIe device DMA into system) metrics:
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* IB write (inbound write): the number of bytes per second that the PCIe device requested to write to main memory through DMA
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* IB read (inbound read): the number of bytes per second that the PCIe device requested to read from main memory through DMA
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Outbound (CPU MMIO to the PCIe device):
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* OB read (outbound write): the number of bytes per second that the CPU requested to write to the PCIe device through MMIO (Memory-mapped I/O)
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* OB write (outbound read): the number of bytes per second that the CPU requested to read from the PCIe device through MMIO
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IOMMU metrics:
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* IOTLB Lookup: IOTLB lookups per second
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* IOTLB Miss: IOTLB misses per second
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* Ctxt Cache Hit: Context cache hits per second
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* 256T Cache Hit: Second Level Page Walk Cache Hits to a 256T page per second
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* 512G Cache Hit: Second Level Page Walk Cache Hits to a 512G page per second
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* 1G Cache Hit: Second Level Page Walk Cache Hits to a 1G page per second
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* 2M Cache Hit: Second Level Page Walk Cache Hits to a 2M page per second
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* IOMMU Mem Access: IOMMU memory accesses per second
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## Event config file:
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pcm-iio tool allows the user to customize the performance events with the config file as a an advanced feature. The event config files are opCode-x-y.txt where x/y is cpu family is model id, for example 6/143 for Sapphire Rapids.
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