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rdementiantonovalexnn
rdementi
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antonovalexnn
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add GNR-D support
Change-Id: I27af4a194862100352796da853fefa768c4f236f Co-authored-by: Alexander Antonov <[email protected]> Co-authored-by: Roman Dementiev <[email protected]>
1 parent 8e99563 commit 894a143

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7 files changed

+257
-90
lines changed

7 files changed

+257
-90
lines changed

‎src/cpucounters.cpp

Lines changed: 58 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,7 @@ void PCM::initCStateSupportTables()
751751
case SPR:
752752
case EMR:
753753
case GNR:
754+
case GNR_D:
754755
case GRR:
755756
case SRF:
756757
PCM_CSTATE_ARRAY(pkgCStateMsr, PCM_PARAM_PROTECT({0, 0, 0x60D, 0, 0, 0, 0x3F9, 0, 0, 0, 0}) );
@@ -810,6 +811,7 @@ void PCM::initCStateSupportTables()
810811
case SPR:
811812
case EMR:
812813
case GNR:
814+
case GNR_D:
813815
case GRR:
814816
case SRF:
815817
PCM_CSTATE_ARRAY(coreCStateMsr, PCM_PARAM_PROTECT({0, 0, 0, 0x3FC, 0, 0, 0x3FD, 0x3FE, 0, 0, 0}) );
@@ -1689,6 +1691,7 @@ bool PCM::detectNominalFrequency()
16891691
|| cpu_family_model == SPR
16901692
|| cpu_family_model == EMR
16911693
|| cpu_family_model == GNR
1694+
|| cpu_family_model == GNR_D
16921695
|| cpu_family_model == SRF
16931696
|| cpu_family_model == GRR
16941697
) ? (100000000ULL) : (133333333ULL);
@@ -1995,6 +1998,7 @@ void PCM::initUncoreObjects()
19951998
case SPR:
19961999
case EMR:
19972000
case GNR:
2001+
case GNR_D:
19982002
case GRR:
19992003
case SRF:
20002004
{
@@ -2182,6 +2186,7 @@ void PCM::initUncorePMUsDirect()
21822186
break;
21832187
case SRF:
21842188
case GNR:
2189+
case GNR_D:
21852190
uncorePMUs[s].resize(1);
21862191
{
21872192
std::vector<std::shared_ptr<HWRegister> > CounterControlRegs{
@@ -2330,6 +2335,7 @@ void PCM::initUncorePMUsDirect()
23302335
case SPR:
23312336
case EMR:
23322337
case GNR:
2338+
case GNR_D:
23332339
case SRF:
23342340
uncorePMUs[s].resize(1);
23352341
addPMUsFromDiscoveryRef(uncorePMUs[s][0][PCU_PMU_ID], SPR_PCU_BOX_TYPE, 0xE);
@@ -2357,6 +2363,7 @@ void PCM::initUncorePMUsDirect()
23572363
addMDFPMUs(SPR_MDF_BOX_TYPE);
23582364
break;
23592365
case GNR:
2366+
case GNR_D:
23602367
case SRF:
23612368
addMDFPMUs(BHS_MDF_BOX_TYPE);
23622369
break;
@@ -2404,6 +2411,7 @@ void PCM::initUncorePMUsDirect()
24042411
switch (cpu_family_model)
24052412
{
24062413
case GNR:
2414+
case GNR_D:
24072415
case GRR:
24082416
case SRF:
24092417
uncorePMUs[s].resize(1);
@@ -2510,6 +2518,7 @@ void PCM::initUncorePMUsDirect()
25102518
}
25112519
break;
25122520
case PCM::GNR:
2521+
case PCM::GNR_D:
25132522
case PCM::SRF:
25142523
for (uint32 s = 0; s < (uint32)num_sockets; ++s)
25152524
{
@@ -2630,7 +2639,7 @@ void PCM::initUncorePMUsDirect()
26302639
{
26312640
static const uint32 IAA_DEV_IDS[] = { 0x0CFE };
26322641
static const uint32 DSA_DEV_IDS[] = { 0x0B25 };
2633-
static const uint32 QAT_DEV_IDS[] = { 0x4940, 0x4942, 0x4944 };
2642+
static const uint32 QAT_DEV_IDS[] = { 0x4940, 0x4942, 0x4944, 0x4946, 0x578a };
26342643
std::vector<std::pair<uint32, uint32> > socket2IAAbus;
26352644
std::vector<std::pair<uint32, uint32> > socket2DSAbus;
26362645
std::vector<std::pair<uint32, uint32> > socket2QATbus;
@@ -2692,7 +2701,7 @@ void PCM::initUncorePMUsDirect()
26922701
std::hex << std::setw(4) << std::setfill('0') << devInfo.domain << ":" <<
26932702
std::hex << std::setw(2) << std::setfill('0') << devInfo.bus << ":" <<
26942703
std::hex << std::setw(2) << std::setfill('0') << devInfo.dev << "." <<
2695-
std::hex << devInfo.func << "/telemetry/control";
2704+
std::hex << devInfo.func << "/telemetry/control";
26962705
qatTLMCTLStr = readSysFS(qat_TLMCTL_sysfs_path.str().c_str(), true);
26972706
if(!qatTLMCTLStr.size()){
26982707
std::cerr << "Warning: IDX - QAT telemetry feature of B:0x" << std::hex << devInfo.bus << ",D:0x" << devInfo.dev << ",F:0x" << devInfo.func \
@@ -2740,6 +2749,7 @@ void PCM::initUncorePMUsDirect()
27402749
IRP_UNIT_CTL = SPR_IRP_UNIT_CTL;
27412750
break;
27422751
case GNR:
2752+
case GNR_D:
27432753
case SRF:
27442754
irpStacks = BHS_M2IOSF_NUM;
27452755
IRP_CTL_REG_OFFSET = BHS_IRP_CTL_REG_OFFSET;
@@ -2881,6 +2891,7 @@ void PCM::initUncorePMUsDirect()
28812891
case PCM::SPR:
28822892
case PCM::EMR:
28832893
case PCM::GNR:
2894+
case PCM::GNR_D:
28842895
case PCM::SRF:
28852896
{
28862897
const auto n_units = (std::min)(uncorePMUDiscovery->getNumBoxes(SPR_CXLCM_BOX_TYPE, s),
@@ -3372,6 +3383,7 @@ bool PCM::isCPUModelSupported(const int model_)
33723383
|| model_ == SPR
33733384
|| model_ == EMR
33743385
|| model_ == GNR
3386+
|| model_ == GNR_D
33753387
|| model_ == GRR
33763388
|| model_ == SRF
33773389
);
@@ -3417,9 +3429,6 @@ bool PCM::checkModel()
34173429
case RPL_3:
34183430
cpu_family_model = RPL;
34193431
break;
3420-
case GNR_D:
3421-
cpu_family_model = GNR;
3422-
break;
34233432
}
34243433

34253434
if(!isCPUModelSupported((int)cpu_family_model))
@@ -3698,6 +3707,7 @@ PCM::ErrorCode PCM::program(const PCM::ProgramMode mode_, const void * parameter
36983707
case SPR:
36993708
case EMR:
37003709
case GNR:
3710+
case GNR_D:
37013711
assert(useSkylakeEvents());
37023712
coreEventDesc[0].event_number = SKL_MEM_LOAD_RETIRED_L3_MISS_EVTNR;
37033713
coreEventDesc[0].umask_value = SKL_MEM_LOAD_RETIRED_L3_MISS_UMASK;
@@ -5023,6 +5033,8 @@ const char * PCM::getUArchCodename(const int32 cpu_family_model_param) const
50235033
return "Emerald Rapids-SP";
50245034
case GNR:
50255035
return "Granite Rapids-SP";
5036+
case GNR_D:
5037+
return "Granite Rapids-D";
50265038
case GRR:
50275039
return "Grand Ridge";
50285040
case SRF:
@@ -7813,6 +7825,19 @@ void ServerUncorePMUs::initRegisterLocations(const PCM * pcm)
78137825
PCM_PCICFG_M3UPI_INIT(5, BHS);
78147826
}
78157827
break;
7828+
case PCM::GNR_D:
7829+
{
7830+
// B2CMI (M2M)
7831+
PCM_PCICFG_M2M_INIT(0, BHS)
7832+
PCM_PCICFG_M2M_INIT(1, BHS)
7833+
PCM_PCICFG_M2M_INIT(2, BHS)
7834+
PCM_PCICFG_M2M_INIT(3, BHS)
7835+
PCM_PCICFG_M2M_INIT(4, BHS)
7836+
PCM_PCICFG_M2M_INIT(5, BHS)
7837+
PCM_PCICFG_M2M_INIT(6, BHS)
7838+
PCM_PCICFG_M2M_INIT(7, BHS)
7839+
}
7840+
break;
78167841
case PCM::SNOWRIDGE:
78177842
{
78187843
PCM_PCICFG_M2M_INIT(0, SERVER)
@@ -8015,6 +8040,7 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm)
80158040
case PCM::SPR:
80168041
case PCM::EMR:
80178042
case PCM::GNR: // B2CMI PMUs
8043+
case PCM::GNR_D:
80188044
case PCM::SRF:
80198045
m2mPMUs.push_back(
80208046
UncorePMU(
@@ -8183,20 +8209,25 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm)
81838209
}
81848210
}
81858211

8186-
auto initBHSiMCPMUs = [&](const size_t numChannelsParam)
8212+
auto initBHSiMCPMUsBase = [&](const size_t base, const size_t numChannelsParam)
81878213
{
81888214
numChannels = (std::min)(numChannelsParam, m2mPMUs.size());
81898215
if (initAndCheckSocket2Ubox0Bus())
81908216
{
81918217
auto memBar = getServerSCFBar(socket2UBOX0bus[socket_].first, socket2UBOX0bus[socket_].second);
81928218
for (int channel = 0; channel < numChannels; ++channel)
81938219
{
8194-
imcPMUs.push_back(createIMCPMU(memBar + BHS_MC_CH_PMON_BASE_ADDR + channel * SERVER_MC_CH_PMON_STEP, SERVER_MC_CH_PMON_SIZE));
8220+
imcPMUs.push_back(createIMCPMU(memBar + base + channel * SERVER_MC_CH_PMON_STEP, SERVER_MC_CH_PMON_SIZE));
81958221
num_imc_channels.push_back(1);
81968222
}
81978223
}
81988224
};
81998225

8226+
auto initBHSiMCPMUs = [&](const size_t numChannelsParam)
8227+
{
8228+
initBHSiMCPMUsBase(BHS_MC_CH_PMON_BASE_ADDR, numChannelsParam);
8229+
};
8230+
82008231
switch (cpu_family_model)
82018232
{
82028233
case PCM::GRR:
@@ -8206,6 +8237,9 @@ void ServerUncorePMUs::initDirect(uint32 socket_, const PCM * pcm)
82068237
case PCM::SRF:
82078238
initBHSiMCPMUs(12);
82088239
break;
8240+
case PCM::GNR_D:
8241+
initBHSiMCPMUsBase(pcm->getCPUStepping() ? GNR_D_B_MC_CH_PMON_BASE_ADDR : GNR_D_A_MC_CH_PMON_BASE_ADDR, 8);
8242+
break;
82098243
}
82108244

82118245
if (imcPMUs.empty())
@@ -8991,6 +9025,7 @@ void ServerUncorePMUs::programServerUncoreMemoryMetrics(const ServerUncoreMemory
89919025
}
89929026
break;
89939027
case PCM::GNR:
9028+
case PCM::GNR_D:
89949029
case PCM::GRR:
89959030
case PCM::SRF:
89969031
if (metrics == PmemMemoryMode)
@@ -9087,6 +9122,7 @@ void ServerUncorePMUs::program()
90879122
EDCCntConfig[EventPosition::WRITE] = MCCntConfig[EventPosition::WRITE] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xf0); // monitor writes on counter 1: CAS_COUNT.WR
90889123
break;
90899124
case PCM::GNR:
9125+
case PCM::GNR_D:
90909126
case PCM::GRR:
90919127
case PCM::SRF:
90929128
MCCntConfig[EventPosition::READ] = MC_CH_PCI_PMON_CTL_EVENT(0x05) + MC_CH_PCI_PMON_CTL_UMASK(0xcf); // monitor reads on counter 0: CAS_COUNT_SCH0.RD
@@ -9220,6 +9256,7 @@ uint64 ServerUncorePMUs::getImcReadsForChannels(uint32 beginChannel, uint32 endC
92209256
switch (cpu_family_model)
92219257
{
92229258
case PCM::GNR:
9259+
case PCM::GNR_D:
92239260
case PCM::GRR:
92249261
case PCM::SRF:
92259262
result += getMCCounter(i, EventPosition::READ2);
@@ -9238,6 +9275,7 @@ uint64 ServerUncorePMUs::getImcWrites()
92389275
switch (cpu_family_model)
92399276
{
92409277
case PCM::GNR:
9278+
case PCM::GNR_D:
92419279
case PCM::GRR:
92429280
case PCM::SRF:
92439281
result += getMCCounter(i, EventPosition::WRITE2);
@@ -9484,6 +9522,7 @@ void ServerUncorePMUs::programM2M()
94849522
cfg[EventPosition::PMM_WRITE] = M2M_PCI_PMON_CTL_EVENT(0x38) + M2M_PCI_PMON_CTL_UMASK(0x80) + UNC_PMON_CTL_UMASK_EXT(0x1C); // UNC_M2M_IMC_WRITES.TO_PMM
94859523
break;
94869524
case PCM::GNR:
9525+
case PCM::GNR_D:
94879526
case PCM::SRF:
94889527
cfg[EventPosition::NM_HIT] = M2M_PCI_PMON_CTL_EVENT(0x1F) + M2M_PCI_PMON_CTL_UMASK(0x0F); // UNC_B2CMI_TAG_HIT.ALL
94899528
cfg[EventPosition::M2M_CLOCKTICKS] = 0; // CLOCKTICKS
@@ -9962,6 +10001,7 @@ uint64 PCM::CX_MSR_PMON_CTRY(uint32 Cbo, uint32 Ctr) const
996210001
case SPR:
996310002
case EMR:
996410003
case GNR:
10004+
case GNR_D:
996510005
case GRR:
996610006
case SRF:
996710007
return SPR_CHA0_MSR_PMON_CTR0 + SPR_CHA_MSR_STEP * Cbo + Ctr;
@@ -9994,6 +10034,7 @@ uint64 PCM::CX_MSR_PMON_BOX_FILTER(uint32 Cbo) const
999410034
case SPR:
999510035
case EMR:
999610036
case GNR:
10037+
case GNR_D:
999710038
case GRR:
999810039
case SRF:
999910040
return SPR_CHA0_MSR_PMON_BOX_FILTER + SPR_CHA_MSR_STEP * Cbo;
@@ -10039,6 +10080,7 @@ uint64 PCM::CX_MSR_PMON_CTLY(uint32 Cbo, uint32 Ctl) const
1003910080
case SPR:
1004010081
case EMR:
1004110082
case GNR:
10083+
case GNR_D:
1004210084
case GRR:
1004310085
case SRF:
1004410086
return SPR_CHA0_MSR_PMON_CTL0 + SPR_CHA_MSR_STEP * Cbo + Ctl;
@@ -10070,6 +10112,7 @@ uint64 PCM::CX_MSR_PMON_BOX_CTL(uint32 Cbo) const
1007010112
case SPR:
1007110113
case EMR:
1007210114
case GNR:
10115+
case GNR_D:
1007310116
case GRR:
1007410117
case SRF:
1007510118
return SPR_CHA0_MSR_PMON_BOX_CTRL + SPR_CHA_MSR_STEP * Cbo;
@@ -10144,6 +10187,7 @@ uint32 PCM::getMaxNumOfCBoxesInternal() const
1014410187
{
1014510188
case GRR:
1014610189
case GNR:
10190+
case GNR_D:
1014710191
case SRF:
1014810192
{
1014910193
const auto MSR_PMON_NUMBER_CBOS = 0x3fed;
@@ -10262,6 +10306,7 @@ void PCM::programIIOCounters(uint64 rawEvents[4], int IIOStack)
1026210306
stacks_count = GRR_M2IOSF_NUM;
1026310307
break;
1026410308
case PCM::GNR:
10309+
case PCM::GNR_D:
1026510310
case PCM::SRF:
1026610311
stacks_count = BHS_M2IOSF_NUM;
1026710312
break;
@@ -10357,6 +10402,7 @@ void PCM::programPCIeEventGroup(eventGroup_t &eventGroup)
1035710402
switch (cpu_family_model)
1035810403
{
1035910404
case PCM::GNR:
10405+
case PCM::GNR_D:
1036010406
case PCM::GRR:
1036110407
case PCM::SRF:
1036210408
case PCM::SPR:
@@ -10410,6 +10456,7 @@ void PCM::programCbo(const uint64 * events, const uint32 opCode, const uint32 nc
1041010456
&& SPR != cpu_family_model
1041110457
&& EMR != cpu_family_model
1041210458
&& GNR != cpu_family_model
10459+
&& GNR_D != cpu_family_model
1041310460
&& SRF != cpu_family_model
1041410461
&& GRR != cpu_family_model
1041510462
)
@@ -10912,6 +10959,7 @@ void UncorePMU::freeze(const uint32 extra)
1091210959
case PCM::SPR:
1091310960
case PCM::EMR:
1091410961
case PCM::GNR:
10962+
case PCM::GNR_D:
1091510963
case PCM::GRR:
1091610964
case PCM::SRF:
1091710965
*unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ;
@@ -10928,6 +10976,7 @@ void UncorePMU::unfreeze(const uint32 extra)
1092810976
case PCM::SPR:
1092910977
case PCM::EMR:
1093010978
case PCM::GNR:
10979+
case PCM::GNR_D:
1093110980
case PCM::GRR:
1093210981
case PCM::SRF:
1093310982
*unitControl = 0;
@@ -10949,6 +10998,7 @@ bool UncorePMU::initFreeze(const uint32 extra, const char* xPICheckMsg)
1094910998
case PCM::SPR:
1095010999
case PCM::EMR:
1095111000
case PCM::GNR:
11001+
case PCM::GNR_D:
1095211002
case PCM::GRR:
1095311003
case PCM::SRF:
1095411004
*unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ; // freeze
@@ -10989,6 +11039,7 @@ void UncorePMU::resetUnfreeze(const uint32 extra)
1098911039
case PCM::SPR:
1099011040
case PCM::EMR:
1099111041
case PCM::GNR:
11042+
case PCM::GNR_D:
1099211043
case PCM::GRR:
1099311044
case PCM::SRF:
1099411045
*unitControl = SPR_UNC_PMON_UNIT_CTL_FRZ + SPR_UNC_PMON_UNIT_CTL_RST_COUNTERS; // freeze and reset counter registers

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