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edwarddavidbakeredwarddavidbaker
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Merge pull request #270 from edwarddavidbaker/sync-platforms
GNR, ARL, LNL: Release event updates
2 parents 65a9b2b + af32903 commit 338d046

13 files changed

+455
-124
lines changed

‎ARL/events/arrowlake_crestmont_core.json‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
5-
"DatePublished": "11/25/2024",
6-
"Version": "1.06",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.07",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.07",
77
"Legend": ""
88
},
99
"Events": [

‎ARL/events/arrowlake_lioncove_core.json‎

Lines changed: 57 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
5-
"DatePublished": "11/25/2024",
6-
"Version": "1.06",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.07",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.07",
77
"Legend": ""
88
},
99
"Events": [
@@ -1411,6 +1411,60 @@
14111411
"PDISTCounter": "NA",
14121412
"Speculative": "1"
14131413
},
1414+
{
1415+
"EventCode": "0x24",
1416+
"UMask": "0x42",
1417+
"UMaskExt": "0x00",
1418+
"EventName": "L2_RQSTS.RFO_HIT",
1419+
"BriefDescription": "RFO requests that hit L2 cache",
1420+
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
1421+
"Counter": "0,1,2,3,4,5,6,7,8,9",
1422+
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
1423+
"SampleAfterValue": "200003",
1424+
"MSRIndex": "0x00",
1425+
"MSRValue": "0x00",
1426+
"Precise": "0",
1427+
"CollectPEBSRecord": "2",
1428+
"TakenAlone": "0",
1429+
"CounterMask": "0",
1430+
"Invert": "0",
1431+
"EdgeDetect": "0",
1432+
"Data_LA": "0",
1433+
"L1_Hit_Indication": "0",
1434+
"Errata": "null",
1435+
"Offcore": "0",
1436+
"Deprecated": "0",
1437+
"Equal": "0",
1438+
"PDISTCounter": "NA",
1439+
"Speculative": "1"
1440+
},
1441+
{
1442+
"EventCode": "0x24",
1443+
"UMask": "0x44",
1444+
"UMaskExt": "0x00",
1445+
"EventName": "L2_RQSTS.CODE_RD_HIT",
1446+
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
1447+
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
1448+
"Counter": "0,1,2,3,4,5,6,7,8,9",
1449+
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
1450+
"SampleAfterValue": "200003",
1451+
"MSRIndex": "0x00",
1452+
"MSRValue": "0x00",
1453+
"Precise": "0",
1454+
"CollectPEBSRecord": "2",
1455+
"TakenAlone": "0",
1456+
"CounterMask": "0",
1457+
"Invert": "0",
1458+
"EdgeDetect": "0",
1459+
"Data_LA": "0",
1460+
"L1_Hit_Indication": "0",
1461+
"Errata": "null",
1462+
"Offcore": "0",
1463+
"Deprecated": "0",
1464+
"Equal": "0",
1465+
"PDISTCounter": "NA",
1466+
"Speculative": "1"
1467+
},
14141468
{
14151469
"EventCode": "0x24",
14161470
"UMask": "0xe1",

‎ARL/events/arrowlake_skymont_core.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
5-
"DatePublished": "11/25/2024",
6-
"Version": "1.06",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.07",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.07",
77
"Legend": ""
88
},
99
"Events": [
@@ -2874,8 +2874,8 @@
28742874
"UMask": "0x6e",
28752875
"UMaskExt": "0x00",
28762876
"EventName": "MACHINE_CLEARS.SLOW",
2877-
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
2878-
"PublicDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
2877+
"BriefDescription": "This event is deprecated.",
2878+
"PublicDescription": "This event is deprecated.",
28792879
"Counter": "0,1,2,3,4,5,6,7",
28802880
"PEBScounters": "0,1,2,3,4,5,6,7",
28812881
"SampleAfterValue": "20003",
@@ -2891,7 +2891,7 @@
28912891
"L1_Hit_Indication": "0",
28922892
"Errata": "null",
28932893
"Offcore": "0",
2894-
"Deprecated": "0",
2894+
"Deprecated": "1",
28952895
"Equal": "0",
28962896
"PDISTCounter": "NA",
28972897
"Speculative": "1"

‎ARL/events/arrowlake_uncore.json‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
33
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
5-
"DatePublished": "11/25/2024",
6-
"Version": "1.06",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.07",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.07",
77
"Legend": ""
88
},
99
"Events": [

‎ARL/events/arrowlake_uncore_experimental.json‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
{
2+
"Header": {
3+
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.07",
5+
"DatePublished": "12/19/2024",
6+
"Version": "1.07",
7+
"Legend": ""
8+
},
9+
"Events": [
10+
{
11+
"Unit": "iMC",
12+
"EventCode": "0x19",
13+
"UMask": "0x00",
14+
"UMaskExt": "0x00",
15+
"EventName": "UNC_M_DRAM_THERMAL_HOT",
16+
"BriefDescription": "Any Rank at Hot state",
17+
"PublicDescription": "Any Rank at Hot state",
18+
"Counter": "0,1,2,3,4",
19+
"CounterMask": "0",
20+
"Invert": "0",
21+
"EdgeDetect": "0",
22+
"Deprecated": "0",
23+
"CounterType": "PGMABLE"
24+
},
25+
{
26+
"Unit": "iMC",
27+
"EventCode": "0x1A",
28+
"UMask": "0x00",
29+
"UMaskExt": "0x00",
30+
"EventName": "UNC_M_DRAM_THERMAL_WARM",
31+
"BriefDescription": "Any Rank at Warm state",
32+
"PublicDescription": "Any Rank at Warm state",
33+
"Counter": "0,1,2,3,4",
34+
"CounterMask": "0",
35+
"Invert": "0",
36+
"EdgeDetect": "0",
37+
"Deprecated": "0",
38+
"CounterType": "PGMABLE"
39+
}
40+
]
41+
}

‎GNR/events/graniterapids_core.json‎

Lines changed: 79 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.04",
5-
"DatePublished": "10/15/2024",
6-
"Version": "1.04",
3+
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.06",
5+
"DatePublished": "01/17/2025",
6+
"Version": "1.06",
77
"Legend": ""
88
},
99
"Events": [
@@ -8982,6 +8982,81 @@
89828982
"PDISTCounter": "0",
89838983
"Speculative": "0"
89848984
},
8985+
{
8986+
"EventCode": "0x2A,0x2B",
8987+
"UMask": "0x01",
8988+
"EventName": "OCR.READS_TO_CORE.SNC_DRAM",
8989+
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
8990+
"PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.",
8991+
"Counter": "0,1,2,3",
8992+
"PEBScounters": "0",
8993+
"SampleAfterValue": "100003",
8994+
"MSRIndex": "0x1a6,0x1a7",
8995+
"MSRValue": "0x708004477",
8996+
"Precise": "0",
8997+
"CollectPEBSRecord": "0",
8998+
"TakenAlone": "0",
8999+
"CounterMask": "0",
9000+
"Invert": "0",
9001+
"EdgeDetect": "0",
9002+
"Data_LA": "0",
9003+
"L1_Hit_Indication": "0",
9004+
"Errata": "null",
9005+
"Offcore": "1",
9006+
"Deprecated": "0",
9007+
"PDISTCounter": "0",
9008+
"Speculative": "0"
9009+
},
9010+
{
9011+
"EventCode": "0x2A,0x2B",
9012+
"UMask": "0x01",
9013+
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
9014+
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
9015+
"PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
9016+
"Counter": "0,1,2,3",
9017+
"PEBScounters": "0",
9018+
"SampleAfterValue": "100003",
9019+
"MSRIndex": "0x1a6,0x1a7",
9020+
"MSRValue": "0x1008004477",
9021+
"Precise": "0",
9022+
"CollectPEBSRecord": "0",
9023+
"TakenAlone": "0",
9024+
"CounterMask": "0",
9025+
"Invert": "0",
9026+
"EdgeDetect": "0",
9027+
"Data_LA": "0",
9028+
"L1_Hit_Indication": "0",
9029+
"Errata": "null",
9030+
"Offcore": "1",
9031+
"Deprecated": "0",
9032+
"PDISTCounter": "0",
9033+
"Speculative": "0"
9034+
},
9035+
{
9036+
"EventCode": "0x2A,0x2B",
9037+
"UMask": "0x01",
9038+
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
9039+
"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
9040+
"PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
9041+
"Counter": "0,1,2,3",
9042+
"PEBScounters": "0",
9043+
"SampleAfterValue": "100003",
9044+
"MSRIndex": "0x1a6,0x1a7",
9045+
"MSRValue": "0x808004477",
9046+
"Precise": "0",
9047+
"CollectPEBSRecord": "0",
9048+
"TakenAlone": "0",
9049+
"CounterMask": "0",
9050+
"Invert": "0",
9051+
"EdgeDetect": "0",
9052+
"Data_LA": "0",
9053+
"L1_Hit_Indication": "0",
9054+
"Errata": "null",
9055+
"Offcore": "1",
9056+
"Deprecated": "0",
9057+
"PDISTCounter": "0",
9058+
"Speculative": "0"
9059+
},
89859060
{
89869061
"EventCode": "0x2A,0x2B",
89879062
"UMask": "0x01",

‎GNR/events/graniterapids_uncore.json‎

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Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.04",
5-
"DatePublished": "10/15/2024",
6-
"Version": "1.04",
3+
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.06",
5+
"DatePublished": "01/17/2025",
6+
"Version": "1.06",
77
"Legend": ""
88
},
99
"Events": [
@@ -897,7 +897,7 @@
897897
"FCMask": "0x00",
898898
"UMaskExt": "0x00CCC7FF",
899899
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
900-
"BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache",
900+
"BriefDescription": "Last level cache prefetch read for ownership from local IA",
901901
"PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
902902
"Counter": "0,1,2,3",
903903
"ELLC": "0",
@@ -915,7 +915,7 @@
915915
"FCMask": "0x00",
916916
"UMaskExt": "0x00C817FF",
917917
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
918-
"BriefDescription": "Data read from local IA that miss the cache",
918+
"BriefDescription": "Data read from local IA",
919919
"PublicDescription": "TOR Inserts : DRds issued by iA Cores",
920920
"Counter": "0,1,2,3",
921921
"ELLC": "0",
@@ -933,7 +933,7 @@
933933
"FCMask": "0x00",
934934
"UMaskExt": "0x00C897FF",
935935
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
936-
"BriefDescription": "Data read prefetch from local IA that miss the cache",
936+
"BriefDescription": "Data read prefetch from local IA",
937937
"PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
938938
"Counter": "0,1,2,3",
939939
"ELLC": "0",
@@ -987,7 +987,7 @@
987987
"FCMask": "0x00",
988988
"UMaskExt": "0x00C816FE",
989989
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
990-
"BriefDescription": "Data read from local IA that miss the cache",
990+
"BriefDescription": "Data read from local IA that miss the cache and targets local memory",
991991
"PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
992992
"Counter": "0,1,2,3",
993993
"ELLC": "0",
@@ -1005,7 +1005,7 @@
10051005
"FCMask": "0x00",
10061006
"UMaskExt": "0x00C8177E",
10071007
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
1008-
"BriefDescription": "Data read from local IA that miss the cache",
1008+
"BriefDescription": "Data read from local IA that miss the cache and targets remote memory",
10091009
"PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
10101010
"Counter": "0,1,2,3",
10111011
"ELLC": "0",
@@ -1023,7 +1023,7 @@
10231023
"FCMask": "0x00",
10241024
"UMaskExt": "0x00C896FE",
10251025
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
1026-
"BriefDescription": "Data read prefetch from local IA that miss the cache",
1026+
"BriefDescription": "Data read prefetch from local IA that miss the cache and targets local memory",
10271027
"PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory",
10281028
"Counter": "0,1,2,3",
10291029
"ELLC": "0",
@@ -1041,7 +1041,7 @@
10411041
"FCMask": "0x00",
10421042
"UMaskExt": "0x00C8977E",
10431043
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
1044-
"BriefDescription": "Data read prefetch from local IA that miss the cache",
1044+
"BriefDescription": "Data read prefetch from local IA that miss the cache and targets remote memory",
10451045
"PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory",
10461046
"Counter": "0,1,2,3",
10471047
"ELLC": "0",
@@ -4417,6 +4417,42 @@
44174417
"FILTER_VALUE": "0",
44184418
"CounterType": "PGMABLE"
44194419
},
4420+
{
4421+
"Unit": "CXLCM",
4422+
"EventCode": "0x41",
4423+
"UMask": "0x10",
4424+
"PortMask": "0x00",
4425+
"FCMask": "0x00",
4426+
"UMaskExt": "0x00000000",
4427+
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
4428+
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
4429+
"PublicDescription": "Number of Allocation to Mem Data Packing buffer",
4430+
"Counter": "4,5,6,7",
4431+
"ELLC": "0",
4432+
"Filter": "na",
4433+
"ExtSel": "0",
4434+
"Deprecated": "0",
4435+
"FILTER_VALUE": "0",
4436+
"CounterType": "PGMABLE"
4437+
},
4438+
{
4439+
"Unit": "CXLDP",
4440+
"EventCode": "0x02",
4441+
"UMask": "0x20",
4442+
"PortMask": "0x00",
4443+
"FCMask": "0x00",
4444+
"UMaskExt": "0x00000000",
4445+
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
4446+
"BriefDescription": "Number of Allocation to M2S Data AGF",
4447+
"PublicDescription": "Number of Allocation to M2S Data AGF",
4448+
"Counter": "0,1,2,3",
4449+
"ELLC": "0",
4450+
"Filter": "na",
4451+
"ExtSel": "0",
4452+
"Deprecated": "0",
4453+
"FILTER_VALUE": "0",
4454+
"CounterType": "PGMABLE"
4455+
},
44204456
{
44214457
"Unit": "B2HOT",
44224458
"EventCode": "0x01",

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