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edwarddavidbakeredwarddavidbaker
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Merge pull request #259 from edwarddavidbaker/sync-platforms
CWF, ARL, LNL, MTL: Sync platforms
2 parents d3f4c2f + ac9a576 commit 64b1867

13 files changed

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lines changed

‎ARL/events/arrowlake_crestmont_core.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.05",
5-
"DatePublished": "10/22/2024",
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"Version": "1.05",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
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"DatePublished": "11/25/2024",
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"Version": "1.06",
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"Legend": ""
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},
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"Events": [
@@ -763,6 +763,87 @@
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x34",
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"UMask": "0x78",
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"UMaskExt": "0x00",
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"EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS",
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"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
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"PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.",
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"Counter": "0,1,2,3,4,5,6,7",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"MSRIndex": "0x00",
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"MSRValue": "0x00",
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"Precise": "0",
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"CollectPEBSRecord": "2",
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"TakenAlone": "0",
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"CounterMask": "0",
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"Invert": "0",
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"EdgeDetect": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x34",
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"UMask": "0x7e",
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"UMaskExt": "0x00",
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"EventName": "MEM_BOUND_STALLS_LOAD.L2_MISS",
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"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
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"PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
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"Counter": "0,1,2,3,4,5,6,7",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"MSRIndex": "0x00",
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"MSRValue": "0x00",
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"Precise": "0",
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"CollectPEBSRecord": "2",
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"TakenAlone": "0",
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"CounterMask": "0",
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"Invert": "0",
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"EdgeDetect": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x34",
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"UMask": "0x7f",
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"UMaskExt": "0x00",
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"EventName": "MEM_BOUND_STALLS_LOAD.ALL",
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"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
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"PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
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"Counter": "0,1,2,3,4,5,6,7",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"MSRIndex": "0x00",
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"MSRValue": "0x00",
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"Precise": "0",
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"CollectPEBSRecord": "2",
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"TakenAlone": "0",
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"CounterMask": "0",
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"Invert": "0",
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"EdgeDetect": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x35",
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"UMask": "0x01",
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x74",
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"UMask": "0x40",
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"UMaskExt": "0x00",
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"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
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"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
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"PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
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"Counter": "0,1,2,3,4,5,6,7",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"MSRIndex": "0x00",
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"MSRValue": "0x00",
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"Precise": "0",
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"CollectPEBSRecord": "2",
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"TakenAlone": "0",
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"CounterMask": "0",
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"Invert": "0",
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"EdgeDetect": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "NA",
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"Speculative": "1"
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},
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{
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"EventCode": "0x75",
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"UMask": "0x04",

‎ARL/events/arrowlake_lioncove_core.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.05",
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"DatePublished": "10/22/2024",
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"Version": "1.05",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
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"DatePublished": "11/25/2024",
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"Version": "1.06",
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"Legend": ""
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},
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"Events": [
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"UMask": "0x01",
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"UMaskExt": "0x00",
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"EventName": "FP_ARITH_DISPATCHED.V0",
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"BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD*/SUB*/MUL/FMA*/DPP.",
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"PublicDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD*/SUB*/MUL/FMA*/DPP.",
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"BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.",
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"PublicDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
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"SampleAfterValue": "2000003",

‎ARL/events/arrowlake_skymont_core.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.05",
5-
"DatePublished": "10/22/2024",
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"Version": "1.05",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
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"DatePublished": "11/25/2024",
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"Version": "1.06",
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"Legend": ""
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},
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"Events": [
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",
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"Data_LA": "0",
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"L1_Hit_Indication": "0",
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"Errata": "null",
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"Offcore": "0",
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"Offcore": "1",
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"Deprecated": "0",
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"Equal": "0",
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"PDISTCounter": "0",

‎ARL/events/arrowlake_uncore.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
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"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.05",
5-
"DatePublished": "10/22/2024",
6-
"Version": "1.05",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.06",
5+
"DatePublished": "11/25/2024",
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"Version": "1.06",
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"Legend": ""
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},
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"Events": [

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