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- const SIMICS_API_ITEMS : & [ & str ; 2461usize ] = & [
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+ const SIMICS_API_ITEMS : & [ & str ; 2480usize ] = & [
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"A20_INTERFACE" ,
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"ABS_POINTER_ACTIVATE_INTERFACE" ,
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"ABS_POINTER_INTERFACE" ,
@@ -269,6 +269,8 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"I2C_SLAVE_INTERFACE" ,
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"I2C_SLAVE_V2_INTERFACE" ,
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"I3C_DAA_SNOOP_INTERFACE" ,
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+ "I3C_HDR_MASTER_INTERFACE" ,
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+ "I3C_HDR_SLAVE_INTERFACE" ,
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"I3C_MASTER_INTERFACE" ,
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"I3C_SLAVE_INTERFACE" ,
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"I8051_INTERRUPT_INTERFACE" ,
@@ -341,6 +343,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"MS1553_TERMINAL_INTERFACE" ,
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"MULTI_LEVEL_SIGNAL_INTERFACE" ,
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"NAND_FLASH_INTERFACE" ,
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+ "NETWORK_BREAKPOINT_INTERFACE" ,
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"NIOS_CACHE_INTERFACE" ,
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"NIOS_CUSTOM_INTERFACE" ,
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"NIOS_EIC_INTERFACE" ,
@@ -432,6 +435,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"RECORDER_INTERFACE" ,
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"RECORDER_V2_INTERFACE" ,
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"REGISTER_BREAKPOINT_INTERFACE" ,
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+ "REGISTER_VIEW_CATALOG_INTERFACE" ,
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"REGISTER_VIEW_INTERFACE" ,
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"REGISTER_VIEW_READ_ONLY_INTERFACE" ,
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"RISCV_CLIC_INTERFACE" ,
@@ -506,6 +510,8 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"SIM_DI_PREFIX_SSE_BIT" ,
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"SIM_DI_PREFIX_SS_BIT" ,
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"SIM_MAJOR_VERSION_DIFF" ,
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+ "SIM_PYOBJECT" ,
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+ "SIM_PYTYPEOBJECT" ,
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"SIM_STC_flush_cache" ,
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"SIM_VERSION" ,
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"SIM_VERSION_4_8" ,
@@ -589,6 +595,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"SIM_ensure_partial_attr_order" ,
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"SIM_event_cancel_step" ,
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"SIM_event_cancel_time" ,
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+ "SIM_event_class_flags" ,
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"SIM_event_find_next_cycle" ,
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"SIM_event_find_next_step" ,
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"SIM_event_find_next_time" ,
@@ -626,6 +633,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"SIM_get_class_port_interface" ,
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"SIM_get_debugger" ,
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"SIM_get_directories" ,
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+ "SIM_get_event_class" ,
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"SIM_get_global_message" ,
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"SIM_get_init_arg_boolean" ,
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"SIM_get_init_arg_string" ,
@@ -1240,13 +1248,14 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"XTENSA_TIE_OUTPUT_QUEUE_INTERFACE" ,
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"XTENSA_WWDT_CONFIG_INTERFACE" ,
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"XTENSA_WWDT_FAULTINFO_INTERFACE" ,
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+ "_" ,
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"_LARGEFILE64_SOURCE" ,
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"_LARGEFILE_SOURCE" ,
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"_POSIX_C_SOURCE" ,
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"_XOPEN_SOURCE" ,
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"__FILE" ,
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"__bool_true_false_are_defined" ,
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- "_mod " ,
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+ "_cpu_instrumentation_entry_t " ,
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"_object" ,
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"_typeobject" ,
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"a20_interface" ,
@@ -1335,6 +1344,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"branch_recorder" ,
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"branch_recorder_direction_t" ,
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"branch_recorder_t" ,
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+ "break_net_cb_t" ,
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"break_string_cb_t" ,
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"break_strings_v2_interface" ,
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"break_strings_v2_interface_t" ,
@@ -1730,6 +1740,8 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"i2c_status_t" ,
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"i3c_ack_t" ,
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"i3c_daa_snoop_interface" ,
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+ "i3c_hdr_master_interface" ,
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+ "i3c_hdr_slave_interface" ,
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"i3c_master_interface" ,
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"i3c_slave_interface" ,
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"ieee_802_3_duplex_mode_t" ,
@@ -1930,6 +1942,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"os_getcwd_nice" ,
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"os_gethostname" ,
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"os_getpid" ,
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+ "os_gettid" ,
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"os_gmtime" ,
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"os_host_ncpus" ,
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"os_host_phys_mem_size" ,
@@ -2029,6 +2042,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"pcie_ats_translation_completion_entry_t" ,
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"pcie_byte_count_ret_t" ,
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"pcie_device_interface" ,
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+ "pcie_ecs_t" ,
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"pcie_error_ret_t" ,
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"pcie_error_t" ,
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"pcie_hotplug_events_interface" ,
@@ -2168,6 +2182,8 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"riscv_imsic_interface" ,
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"riscv_imsic_interface_t" ,
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"riscv_instruction_action_interface" ,
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+ "riscv_io_error_ret_t" ,
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+ "riscv_io_error_t" ,
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"riscv_memory_transaction" ,
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"riscv_memory_transaction_t" ,
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"riscv_reset_cb_t" ,
@@ -2181,6 +2197,7 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"sb_addesc" ,
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"sb_addfmt" ,
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"sb_detach" ,
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+ "sb_escape" ,
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"sb_fmt" ,
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"sb_free" ,
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"sb_new" ,
@@ -2298,6 +2315,8 @@ const SIMICS_API_ITEMS: &[&str; 2461usize] = &[
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"transaction_issue_cb_t" ,
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"transaction_subscribe_interface" ,
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"transaction_t" ,
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+ "transaction_target_type_ret_t" ,
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+ "transaction_target_type_t" ,
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"transaction_trace_atom_access" ,
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"transaction_trace_atom_access_t" ,
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"translate_interface" ,
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