Add arm architecture (#76)

novafacing · web-flow · commit 5da36065e378 · 2024-04-25T09:49:19.000-07:00
diff --git a/Cargo.toml b/Cargo.toml
@@ -75,6 +75,7 @@ num-traits = "0.2.18"
 num-derive = "0.4.2"
 tracing-subscriber = "0.3.18"
 tracing = { version = "0.1.40", features = ["log"] }
+yaxpeax-arm = "0.2.5"
 
 [dev-dependencies]
 simics-test = { path = "simics-rs/simics-test" }
diff --git a/src/arch/aarch64.rs b/src/arch/aarch64.rs
diff --git a/src/arch/arm.rs b/src/arch/arm.rs
diff --git a/src/arch/mod.rs b/src/arch/mod.rs
@@ -4,6 +4,7 @@
 //! Architecture specific data and definitions
 
 use self::{
+    aarch64::AArch64ArchitectureOperations, arm::ARMArchitectureOperations,
     risc_v::RISCVArchitectureOperations, x86::X86ArchitectureOperations,
     x86_64::X86_64ArchitectureOperations,
 };
@@ -24,6 +25,8 @@ use simics::{
 };
 use std::{fmt::Debug, str::FromStr};
 
+pub mod aarch64;
+pub mod arm;
 pub mod risc_v;
 pub mod x86;
 pub mod x86_64;
@@ -37,6 +40,10 @@ pub(crate) enum ArchitectureHint {
     I386,
     /// The architecture is RISCV
     Riscv,
+    /// The architecture is arm
+    Arm,
+    /// The architecture is aarch64
+    Aarch64,
 }
 
 impl FromStr for ArchitectureHint {
@@ -47,6 +54,8 @@ impl FromStr for ArchitectureHint {
             "x86-64" => Self::X86_64,
             "i386" | "i486" | "i586" | "i686" | "ia-32" | "x86" => Self::I386,
             "riscv" | "risc-v" | "riscv32" | "riscv64" => Self::Riscv,
+            "armv4" | "armv5" | "armv6" | "armv7" | "arm" | "arm32" => Self::Arm,
+            "aarch64" | "armv8" | "arm64" => Self::Aarch64,
             _ => bail!("Unknown hint: {}", s),
         })
     }
@@ -58,6 +67,8 @@ impl From<ArchitectureHint> for AttrValueType {
             ArchitectureHint::X86_64 => "x86-64",
             ArchitectureHint::I386 => "i386",
             ArchitectureHint::Riscv => "risc-v",
+            ArchitectureHint::Arm => "arm",
+            ArchitectureHint::Aarch64 => "aarch64",
         }
         .into()
     }
@@ -76,6 +87,12 @@ impl ArchitectureHint {
             ArchitectureHint::Riscv => {
                 Architecture::Riscv(RISCVArchitectureOperations::new_unchecked(cpu)?)
             }
+            ArchitectureHint::Arm => {
+                Architecture::Arm(ARMArchitectureOperations::new_unchecked(cpu)?)
+            }
+            ArchitectureHint::Aarch64 => {
+                Architecture::Aarch64(AArch64ArchitectureOperations::new_unchecked(cpu)?)
+            }
         })
     }
 }
@@ -87,6 +104,10 @@ pub(crate) enum Architecture {
     I386(X86ArchitectureOperations),
     /// The RISC-V architecture
     Riscv(RISCVArchitectureOperations),
+    /// The ARM architecture (v7 and below)
+    Arm(ARMArchitectureOperations),
+    /// The AARCH64 architecture (v8 and above)
+    Aarch64(AArch64ArchitectureOperations),
 }
 
 impl Debug for Architecture {
@@ -98,6 +119,8 @@ impl Debug for Architecture {
                 Architecture::X86_64(_) => "x86-64",
                 Architecture::I386(_) => "i386",
                 Architecture::Riscv(_) => "risc-v",
+                Architecture::Arm(_) => "arm",
+                Architecture::Aarch64(_) => "aarch64",
             }
         )
     }
@@ -513,6 +536,10 @@ impl ArchitectureOperations for Architecture {
             Ok(Self::I386(x86))
         } else if let Ok(riscv) = RISCVArchitectureOperations::new(cpu) {
             Ok(Self::Riscv(riscv))
+        } else if let Ok(arm) = ARMArchitectureOperations::new(cpu) {
+            Ok(Self::Arm(arm))
+        } else if let Ok(aarch64) = AArch64ArchitectureOperations::new(cpu) {
+            Ok(Self::Aarch64(aarch64))
         } else {
             bail!("Unsupported architecture");
         }
@@ -523,6 +550,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.cpu(),
             Architecture::I386(i386) => i386.cpu(),
             Architecture::Riscv(riscv) => riscv.cpu(),
+            Architecture::Arm(arm) => arm.cpu(),
+            Architecture::Aarch64(aarch64) => aarch64.cpu(),
         }
     }
 
@@ -531,6 +560,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.disassembler(),
             Architecture::I386(i386) => i386.disassembler(),
             Architecture::Riscv(riscv) => riscv.disassembler(),
+            Architecture::Arm(arm) => arm.disassembler(),
+            Architecture::Aarch64(aarch64) => aarch64.disassembler(),
         }
     }
 
@@ -539,6 +570,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.int_register(),
             Architecture::I386(i386) => i386.int_register(),
             Architecture::Riscv(riscv) => riscv.int_register(),
+            Architecture::Arm(arm) => arm.int_register(),
+            Architecture::Aarch64(aarch64) => aarch64.int_register(),
         }
     }
 
@@ -547,6 +580,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.processor_info_v2(),
             Architecture::I386(i386) => i386.processor_info_v2(),
             Architecture::Riscv(riscv) => riscv.processor_info_v2(),
+            Architecture::Arm(arm) => arm.processor_info_v2(),
+            Architecture::Aarch64(aarch64) => aarch64.processor_info_v2(),
         }
     }
 
@@ -555,6 +590,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.cpu_instruction_query(),
             Architecture::I386(i386) => i386.cpu_instruction_query(),
             Architecture::Riscv(riscv) => riscv.cpu_instruction_query(),
+            Architecture::Arm(arm) => arm.cpu_instruction_query(),
+            Architecture::Aarch64(aarch64) => aarch64.cpu_instruction_query(),
         }
     }
 
@@ -563,6 +600,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.cpu_instrumentation_subscribe(),
             Architecture::I386(i386) => i386.cpu_instrumentation_subscribe(),
             Architecture::Riscv(riscv) => riscv.cpu_instrumentation_subscribe(),
+            Architecture::Arm(arm) => arm.cpu_instrumentation_subscribe(),
+            Architecture::Aarch64(aarch64) => aarch64.cpu_instrumentation_subscribe(),
         }
     }
 
@@ -571,6 +610,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.cycle(),
             Architecture::I386(i386) => i386.cycle(),
             Architecture::Riscv(riscv) => riscv.cycle(),
+            Architecture::Arm(arm) => arm.cycle(),
+            Architecture::Aarch64(aarch64) => aarch64.cycle(),
         }
     }
 
@@ -579,6 +620,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.get_magic_index_selector(),
             Architecture::I386(i386) => i386.get_magic_index_selector(),
             Architecture::Riscv(riscv) => riscv.get_magic_index_selector(),
+            Architecture::Arm(arm) => arm.get_magic_index_selector(),
+            Architecture::Aarch64(aarch64) => aarch64.get_magic_index_selector(),
         }
     }
 
@@ -587,6 +630,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_ptr(),
             Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_ptr(),
             Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_ptr(),
+            Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_ptr(),
+            Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_ptr(),
         }
     }
 
@@ -595,6 +640,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_val(),
             Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_val(),
             Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_val(),
+            Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_val(),
+            Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_val(),
         }
     }
 
@@ -603,6 +650,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_ptr(),
             Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_ptr(),
             Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_ptr(),
+            Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_ptr_val(),
+            Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_ptr_val(),
         }
     }
 
@@ -611,6 +660,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.get_manual_start_info(info),
             Architecture::I386(i386) => i386.get_manual_start_info(info),
             Architecture::Riscv(riscv) => riscv.get_manual_start_info(info),
+            Architecture::Arm(arm) => arm.get_manual_start_info(info),
+            Architecture::Aarch64(aarch64) => aarch64.get_manual_start_info(info),
         }
     }
 
@@ -619,6 +670,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.write_start(testcase, info),
             Architecture::I386(i386) => i386.write_start(testcase, info),
             Architecture::Riscv(riscv) => riscv.write_start(testcase, info),
+            Architecture::Arm(arm) => arm.write_start(testcase, info),
+            Architecture::Aarch64(aarch64) => aarch64.write_start(testcase, info),
         }
     }
 
@@ -627,6 +680,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.trace_pc(instruction_query),
             Architecture::I386(i386) => i386.trace_pc(instruction_query),
             Architecture::Riscv(riscv) => riscv.trace_pc(instruction_query),
+            Architecture::Arm(arm) => arm.trace_pc(instruction_query),
+            Architecture::Aarch64(aarch64) => aarch64.trace_pc(instruction_query),
         }
     }
 
@@ -635,6 +690,8 @@ impl ArchitectureOperations for Architecture {
             Architecture::X86_64(x86_64) => x86_64.trace_cmp(instruction_query),
             Architecture::I386(i386) => i386.trace_cmp(instruction_query),
             Architecture::Riscv(riscv) => riscv.trace_cmp(instruction_query),
+            Architecture::Arm(arm) => arm.trace_cmp(instruction_query),
+            Architecture::Aarch64(aarch64) => aarch64.trace_cmp(instruction_query),
         }
     }
 }
diff --git a/src/arch/x86.rs b/src/arch/x86.rs
@@ -730,6 +730,10 @@ impl X86ArchitectureOperations {
                         .to_le_bytes();
                 Ok(CmpValue::U64(u64::from_le_bytes(bytes)))
             }
+            _ => {
+                // There are other types but they are never emitted on x86
+                bail!("Unsupported expression type");
+            }
         }
     }
 }
diff --git a/src/arch/x86_64.rs b/src/arch/x86_64.rs
@@ -704,6 +704,10 @@ impl X86_64ArchitectureOperations {
                         .to_le_bytes();
                 Ok(CmpValue::U64(u64::from_le_bytes(bytes)))
             }
+            _ => {
+                // There are other types but they are never emitted on x86_64
+                bail!("Unsupported expression type")
+            }
         }
     }
 }
diff --git a/src/tracer/mod.rs b/src/tracer/mod.rs
@@ -18,12 +18,22 @@ use typed_builder::TypedBuilder;
 
 use crate::{arch::ArchitectureOperations, Tsffs};
 
+#[derive(Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub(crate) enum CmpExprShift {
+    Lsl,
+    Lsr,
+    Asr,
+    Ror,
+}
+
 #[derive(Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
 pub(crate) enum CmpExpr {
     Deref((Box<CmpExpr>, Option<u8>)),
     Reg((String, u8)),
     Mul((Box<CmpExpr>, Box<CmpExpr>)),
     Add((Box<CmpExpr>, Box<CmpExpr>)),
+    Sub((Box<CmpExpr>, Box<CmpExpr>)),
+    Shift((Box<CmpExpr>, Box<CmpExpr>, CmpExprShift)),
     U8(u8),
     I8(i8),
     U16(u16),

Original file line number	Diff line number	Diff line change
`@@ -4,6 +4,7 @@`
`4`	`4`	`//! Architecture specific data and definitions`
`5`	`5`
`6`	`6`	`use self::{`
	`7`	`+ aarch64::AArch64ArchitectureOperations, arm::ARMArchitectureOperations,`
`7`	`8`	`risc_v::RISCVArchitectureOperations, x86::X86ArchitectureOperations,`
`8`	`9`	`x86_64::X86_64ArchitectureOperations,`
`9`	`10`	`};`
`@@ -24,6 +25,8 @@ use simics::{`
`24`	`25`	`};`
`25`	`26`	`use std::{fmt::Debug, str::FromStr};`
`26`	`27`
	`28`	`+pub mod aarch64;`
	`29`	`+pub mod arm;`
`27`	`30`	`pub mod risc_v;`
`28`	`31`	`pub mod x86;`
`29`	`32`	`pub mod x86_64;`
`@@ -37,6 +40,10 @@ pub(crate) enum ArchitectureHint {`
`37`	`40`	`I386,`
`38`	`41`	`/// The architecture is RISCV`
`39`	`42`	`Riscv,`
	`43`	`+ /// The architecture is arm`
	`44`	`+ Arm,`
	`45`	`+ /// The architecture is aarch64`
	`46`	`+ Aarch64,`
`40`	`47`	`}`
`41`	`48`
`42`	`49`	`impl FromStr for ArchitectureHint {`
`@@ -47,6 +54,8 @@ impl FromStr for ArchitectureHint {`
`47`	`54`	`"x86-64" => Self::X86_64,`
`48`	`55`	`"i386" \| "i486" \| "i586" \| "i686" \| "ia-32" \| "x86" => Self::I386,`
`49`	`56`	`"riscv" \| "risc-v" \| "riscv32" \| "riscv64" => Self::Riscv,`
	`57`	`+ "armv4" \| "armv5" \| "armv6" \| "armv7" \| "arm" \| "arm32" => Self::Arm,`
	`58`	`+ "aarch64" \| "armv8" \| "arm64" => Self::Aarch64,`
`50`	`59`	`_ => bail!("Unknown hint: {}", s),`
`51`	`60`	`})`
`52`	`61`	`}`
`@@ -58,6 +67,8 @@ impl From<ArchitectureHint> for AttrValueType {`
`58`	`67`	`ArchitectureHint::X86_64 => "x86-64",`
`59`	`68`	`ArchitectureHint::I386 => "i386",`
`60`	`69`	`ArchitectureHint::Riscv => "risc-v",`
	`70`	`+ ArchitectureHint::Arm => "arm",`
	`71`	`+ ArchitectureHint::Aarch64 => "aarch64",`
`61`	`72`	`}`
`62`	`73`	`.into()`
`63`	`74`	`}`
`@@ -76,6 +87,12 @@ impl ArchitectureHint {`
`76`	`87`	`ArchitectureHint::Riscv => {`
`77`	`88`	`Architecture::Riscv(RISCVArchitectureOperations::new_unchecked(cpu)?)`
`78`	`89`	`}`
	`90`	`+ ArchitectureHint::Arm => {`
	`91`	`+ Architecture::Arm(ARMArchitectureOperations::new_unchecked(cpu)?)`
	`92`	`+ }`
	`93`	`+ ArchitectureHint::Aarch64 => {`
	`94`	`+ Architecture::Aarch64(AArch64ArchitectureOperations::new_unchecked(cpu)?)`
	`95`	`+ }`
`79`	`96`	`})`
`80`	`97`	`}`
`81`	`98`	`}`
`@@ -87,6 +104,10 @@ pub(crate) enum Architecture {`
`87`	`104`	`I386(X86ArchitectureOperations),`
`88`	`105`	`/// The RISC-V architecture`
`89`	`106`	`Riscv(RISCVArchitectureOperations),`
	`107`	`+ /// The ARM architecture (v7 and below)`
	`108`	`+ Arm(ARMArchitectureOperations),`
	`109`	`+ /// The AARCH64 architecture (v8 and above)`
	`110`	`+ Aarch64(AArch64ArchitectureOperations),`
`90`	`111`	`}`
`91`	`112`
`92`	`113`	`impl Debug for Architecture {`
`@@ -98,6 +119,8 @@ impl Debug for Architecture {`
`98`	`119`	`Architecture::X86_64(_) => "x86-64",`
`99`	`120`	`Architecture::I386(_) => "i386",`
`100`	`121`	`Architecture::Riscv(_) => "risc-v",`
	`122`	`+ Architecture::Arm(_) => "arm",`
	`123`	`+ Architecture::Aarch64(_) => "aarch64",`
`101`	`124`	`}`
`102`	`125`	`)`
`103`	`126`	`}`
`@@ -513,6 +536,10 @@ impl ArchitectureOperations for Architecture {`
`513`	`536`	`Ok(Self::I386(x86))`
`514`	`537`	`} else if let Ok(riscv) = RISCVArchitectureOperations::new(cpu) {`
`515`	`538`	`Ok(Self::Riscv(riscv))`
	`539`	`+ } else if let Ok(arm) = ARMArchitectureOperations::new(cpu) {`
	`540`	`+ Ok(Self::Arm(arm))`
	`541`	`+ } else if let Ok(aarch64) = AArch64ArchitectureOperations::new(cpu) {`
	`542`	`+ Ok(Self::Aarch64(aarch64))`
`516`	`543`	`} else {`
`517`	`544`	`bail!("Unsupported architecture");`
`518`	`545`	`}`
`@@ -523,6 +550,8 @@ impl ArchitectureOperations for Architecture {`
`523`	`550`	`Architecture::X86_64(x86_64) => x86_64.cpu(),`
`524`	`551`	`Architecture::I386(i386) => i386.cpu(),`
`525`	`552`	`Architecture::Riscv(riscv) => riscv.cpu(),`
	`553`	`+ Architecture::Arm(arm) => arm.cpu(),`
	`554`	`+ Architecture::Aarch64(aarch64) => aarch64.cpu(),`
`526`	`555`	`}`
`527`	`556`	`}`
`528`	`557`
`@@ -531,6 +560,8 @@ impl ArchitectureOperations for Architecture {`
`531`	`560`	`Architecture::X86_64(x86_64) => x86_64.disassembler(),`
`532`	`561`	`Architecture::I386(i386) => i386.disassembler(),`
`533`	`562`	`Architecture::Riscv(riscv) => riscv.disassembler(),`
	`563`	`+ Architecture::Arm(arm) => arm.disassembler(),`
	`564`	`+ Architecture::Aarch64(aarch64) => aarch64.disassembler(),`
`534`	`565`	`}`
`535`	`566`	`}`
`536`	`567`
`@@ -539,6 +570,8 @@ impl ArchitectureOperations for Architecture {`
`539`	`570`	`Architecture::X86_64(x86_64) => x86_64.int_register(),`
`540`	`571`	`Architecture::I386(i386) => i386.int_register(),`
`541`	`572`	`Architecture::Riscv(riscv) => riscv.int_register(),`
	`573`	`+ Architecture::Arm(arm) => arm.int_register(),`
	`574`	`+ Architecture::Aarch64(aarch64) => aarch64.int_register(),`
`542`	`575`	`}`
`543`	`576`	`}`
`544`	`577`
`@@ -547,6 +580,8 @@ impl ArchitectureOperations for Architecture {`
`547`	`580`	`Architecture::X86_64(x86_64) => x86_64.processor_info_v2(),`
`548`	`581`	`Architecture::I386(i386) => i386.processor_info_v2(),`
`549`	`582`	`Architecture::Riscv(riscv) => riscv.processor_info_v2(),`
	`583`	`+ Architecture::Arm(arm) => arm.processor_info_v2(),`
	`584`	`+ Architecture::Aarch64(aarch64) => aarch64.processor_info_v2(),`
`550`	`585`	`}`
`551`	`586`	`}`
`552`	`587`
`@@ -555,6 +590,8 @@ impl ArchitectureOperations for Architecture {`
`555`	`590`	`Architecture::X86_64(x86_64) => x86_64.cpu_instruction_query(),`
`556`	`591`	`Architecture::I386(i386) => i386.cpu_instruction_query(),`
`557`	`592`	`Architecture::Riscv(riscv) => riscv.cpu_instruction_query(),`
	`593`	`+ Architecture::Arm(arm) => arm.cpu_instruction_query(),`
	`594`	`+ Architecture::Aarch64(aarch64) => aarch64.cpu_instruction_query(),`
`558`	`595`	`}`
`559`	`596`	`}`
`560`	`597`
`@@ -563,6 +600,8 @@ impl ArchitectureOperations for Architecture {`
`563`	`600`	`Architecture::X86_64(x86_64) => x86_64.cpu_instrumentation_subscribe(),`
`564`	`601`	`Architecture::I386(i386) => i386.cpu_instrumentation_subscribe(),`
`565`	`602`	`Architecture::Riscv(riscv) => riscv.cpu_instrumentation_subscribe(),`
	`603`	`+ Architecture::Arm(arm) => arm.cpu_instrumentation_subscribe(),`
	`604`	`+ Architecture::Aarch64(aarch64) => aarch64.cpu_instrumentation_subscribe(),`
`566`	`605`	`}`
`567`	`606`	`}`
`568`	`607`
`@@ -571,6 +610,8 @@ impl ArchitectureOperations for Architecture {`
`571`	`610`	`Architecture::X86_64(x86_64) => x86_64.cycle(),`
`572`	`611`	`Architecture::I386(i386) => i386.cycle(),`
`573`	`612`	`Architecture::Riscv(riscv) => riscv.cycle(),`
	`613`	`+ Architecture::Arm(arm) => arm.cycle(),`
	`614`	`+ Architecture::Aarch64(aarch64) => aarch64.cycle(),`
`574`	`615`	`}`
`575`	`616`	`}`
`576`	`617`
`@@ -579,6 +620,8 @@ impl ArchitectureOperations for Architecture {`
`579`	`620`	`Architecture::X86_64(x86_64) => x86_64.get_magic_index_selector(),`
`580`	`621`	`Architecture::I386(i386) => i386.get_magic_index_selector(),`
`581`	`622`	`Architecture::Riscv(riscv) => riscv.get_magic_index_selector(),`
	`623`	`+ Architecture::Arm(arm) => arm.get_magic_index_selector(),`
	`624`	`+ Architecture::Aarch64(aarch64) => aarch64.get_magic_index_selector(),`
`582`	`625`	`}`
`583`	`626`	`}`
`584`	`627`
`@@ -587,6 +630,8 @@ impl ArchitectureOperations for Architecture {`
`587`	`630`	`Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_ptr(),`
`588`	`631`	`Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_ptr(),`
`589`	`632`	`Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_ptr(),`
	`633`	`+ Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_ptr(),`
	`634`	`+ Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_ptr(),`
`590`	`635`	`}`
`591`	`636`	`}`
`592`	`637`
`@@ -595,6 +640,8 @@ impl ArchitectureOperations for Architecture {`
`595`	`640`	`Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_val(),`
`596`	`641`	`Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_val(),`
`597`	`642`	`Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_val(),`
	`643`	`+ Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_val(),`
	`644`	`+ Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_val(),`
`598`	`645`	`}`
`599`	`646`	`}`
`600`	`647`
`@@ -603,6 +650,8 @@ impl ArchitectureOperations for Architecture {`
`603`	`650`	`Architecture::X86_64(x86_64) => x86_64.get_magic_start_buffer_ptr_size_ptr(),`
`604`	`651`	`Architecture::I386(i386) => i386.get_magic_start_buffer_ptr_size_ptr(),`
`605`	`652`	`Architecture::Riscv(riscv) => riscv.get_magic_start_buffer_ptr_size_ptr(),`
	`653`	`+ Architecture::Arm(arm) => arm.get_magic_start_buffer_ptr_size_ptr_val(),`
	`654`	`+ Architecture::Aarch64(aarch64) => aarch64.get_magic_start_buffer_ptr_size_ptr_val(),`
`606`	`655`	`}`
`607`	`656`	`}`
`608`	`657`
`@@ -611,6 +660,8 @@ impl ArchitectureOperations for Architecture {`
`611`	`660`	`Architecture::X86_64(x86_64) => x86_64.get_manual_start_info(info),`
`612`	`661`	`Architecture::I386(i386) => i386.get_manual_start_info(info),`
`613`	`662`	`Architecture::Riscv(riscv) => riscv.get_manual_start_info(info),`
	`663`	`+ Architecture::Arm(arm) => arm.get_manual_start_info(info),`
	`664`	`+ Architecture::Aarch64(aarch64) => aarch64.get_manual_start_info(info),`
`614`	`665`	`}`
`615`	`666`	`}`
`616`	`667`
`@@ -619,6 +670,8 @@ impl ArchitectureOperations for Architecture {`
`619`	`670`	`Architecture::X86_64(x86_64) => x86_64.write_start(testcase, info),`
`620`	`671`	`Architecture::I386(i386) => i386.write_start(testcase, info),`
`621`	`672`	`Architecture::Riscv(riscv) => riscv.write_start(testcase, info),`
	`673`	`+ Architecture::Arm(arm) => arm.write_start(testcase, info),`
	`674`	`+ Architecture::Aarch64(aarch64) => aarch64.write_start(testcase, info),`
`622`	`675`	`}`
`623`	`676`	`}`
`624`	`677`
`@@ -627,6 +680,8 @@ impl ArchitectureOperations for Architecture {`
`627`	`680`	`Architecture::X86_64(x86_64) => x86_64.trace_pc(instruction_query),`
`628`	`681`	`Architecture::I386(i386) => i386.trace_pc(instruction_query),`
`629`	`682`	`Architecture::Riscv(riscv) => riscv.trace_pc(instruction_query),`
	`683`	`+ Architecture::Arm(arm) => arm.trace_pc(instruction_query),`
	`684`	`+ Architecture::Aarch64(aarch64) => aarch64.trace_pc(instruction_query),`
`630`	`685`	`}`
`631`	`686`	`}`
`632`	`687`
`@@ -635,6 +690,8 @@ impl ArchitectureOperations for Architecture {`
`635`	`690`	`Architecture::X86_64(x86_64) => x86_64.trace_cmp(instruction_query),`
`636`	`691`	`Architecture::I386(i386) => i386.trace_cmp(instruction_query),`
`637`	`692`	`Architecture::Riscv(riscv) => riscv.trace_cmp(instruction_query),`
	`693`	`+ Architecture::Arm(arm) => arm.trace_cmp(instruction_query),`
	`694`	`+ Architecture::Aarch64(aarch64) => aarch64.trace_cmp(instruction_query),`
`638`	`695`	`}`
`639`	`696`	`}`
`640`	`697`	`}`
Original file line number	Diff line number	Diff line change
`@@ -730,6 +730,10 @@ impl X86ArchitectureOperations {`
`730`	`730`	`.to_le_bytes();`
`731`	`731`	`Ok(CmpValue::U64(u64::from_le_bytes(bytes)))`
`732`	`732`	`}`
	`733`	`+ _ => {`
	`734`	`+ // There are other types but they are never emitted on x86`
	`735`	`+ bail!("Unsupported expression type");`
	`736`	`+ }`
`733`	`737`	`}`
`734`	`738`	`}`
`735`	`739`	`}`
Original file line number	Diff line number	Diff line change
`@@ -704,6 +704,10 @@ impl X86_64ArchitectureOperations {`
`704`	`704`	`.to_le_bytes();`
`705`	`705`	`Ok(CmpValue::U64(u64::from_le_bytes(bytes)))`
`706`	`706`	`}`
	`707`	`+ _ => {`
	`708`	`+ // There are other types but they are never emitted on x86_64`
	`709`	`+ bail!("Unsupported expression type")`
	`710`	`+ }`
`707`	`711`	`}`
`708`	`712`	`}`
`709`	`713`	`}`