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Fix register destinations for aarch64 harness to match arch/aarch64.rs and add clobber lists for ARM and aarch64 (#217)
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3 files changed

+65
-45
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3 files changed

+65
-45
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‎harness/tsffs-gcc-aarch64.h‎

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// SPDX-License-Identifier: Apache-2.0
33

44
/// Definitions and macros for compiled-in harnessing of C and C++ target
5-
/// software for the RISC-V (32-bit) architecture
5+
/// software for the aarch64 architecture
66

77
#ifndef TSFFS_H
88
#define TSFFS_H
@@ -40,10 +40,11 @@
4040
/// * `arg0` - The value to place in register `r10`
4141
#define __orr_extended1(value, arg0) \
4242
__asm__ __volatile__( \
43-
"mov x28, %0; orr x" __tostring(value) ", x" __tostring( \
43+
"mov x10, %0; orr x" __tostring(value) ", x" __tostring( \
4444
value) ", x" __tostring(value) \
4545
: \
46-
: "g"(arg0));
46+
: "g"((unsigned long long)arg0) \
47+
: "x10");
4748

4849
/// __orr_extended2
4950
///
@@ -58,10 +59,11 @@
5859
/// * `arg1` - The value to place in register `r9`
5960
#define __orr_extended2(value, arg0, arg1) \
6061
__asm__ __volatile__( \
61-
"mov x28, %0; mov x27, %1; orr x" __tostring(value) ", x" __tostring( \
62+
"mov x10, %0; mov x9, %1; orr x" __tostring(value) ", x" __tostring( \
6263
value) ", x" __tostring(value) \
6364
: \
64-
: "r"(arg0), "r"(arg1));
65+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1) \
66+
: "x10", "x9");
6567

6668
/// __orr_extended3
6769
///
@@ -75,12 +77,14 @@
7577
/// * `arg0` - The value to place in register `r10`
7678
/// * `arg1` - The value to place in register `r9`
7779
/// * `arg2` - The value to place in register `r8`
78-
#define __orr_extended3(value, arg0, arg1, arg2) \
79-
__asm__ __volatile__( \
80-
"mov x28, %0; mov x27, %1; mov x26, %2; orr x" __tostring( \
81-
value) ", x" __tostring(value) ", x" __tostring(value) \
82-
: \
83-
: "r"(arg0), "r"(arg1), "r"(arg2));
80+
#define __orr_extended3(value, arg0, arg1, arg2) \
81+
__asm__ __volatile__( \
82+
"mov x10, %0; mov x9, %1; mov x8, %2; orr x" __tostring( \
83+
value) ", x" __tostring(value) ", x" __tostring(value) \
84+
: \
85+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1), \
86+
"r"((unsigned long long)arg2) \
87+
: "x10", "x9");
8488

8589
/// __orr_extended4
8690
///
@@ -97,16 +101,18 @@
97101
/// * `arg3` - The value to place in register `r7`
98102
#define __orr_extended4(value, arg0, arg1, arg2, arg3) \
99103
__asm__ __volatile__( \
100-
"mov x28, %0; mov x27, %1; mov x26, %2; mov x25, %3; " \
104+
"mov x10, %0; mov x9, %1; mov x8, %2; mov x7, %3; " \
101105
"orr x" __tostring(value) ", x" __tostring(value) ", x" __tostring( \
102106
value) \
103107
: \
104-
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3));
108+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1), \
109+
"r"((unsigned long long)arg2), "r"((unsigned long long)arg3) \
110+
: "x10", "x9");
105111

106112
/// The default index number used for magic instructions. All magic instructions
107113
/// support multiple start and stop indices, which defaults to 0 if not
108114
/// specified.
109-
#define DEFAULT_INDEX (0x0000U)
115+
#define DEFAULT_INDEX (0x0000)
110116

111117
/// Pseudo-hypercall number to signal the fuzzer to use the first argument to
112118
/// the magic instruction as the pointer to the testcase buffer and the second
@@ -178,7 +184,7 @@
178184
/// ```
179185
/// unsigned char buffer[1024];
180186
/// size_t size;
181-
/// HARNESS_START_INDEX(0x0001U, buffer, &size);
187+
/// HARNESS_START_INDEX(0x0001, buffer, &size);
182188
/// ```
183189
#define HARNESS_START_INDEX(start_index, buffer, size_ptr) \
184190
do { \
@@ -254,7 +260,7 @@
254260
///
255261
/// ```
256262
/// unsigned char buffer[1024];
257-
/// HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(0x0001U, buffer, 1024);
263+
/// HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(0x0001, buffer, 1024);
258264
/// ```
259265
#define HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(start_index, buffer, max_size) \
260266
do { \
@@ -388,7 +394,7 @@
388394
/// # Example
389395
///
390396
/// ```
391-
/// HARNESS_STOP_INDEX(0x0001U);
397+
/// HARNESS_STOP_INDEX(0x0001);
392398
/// ```
393399
#define HARNESS_STOP_INDEX(stop_index) \
394400
do { \
@@ -437,7 +443,7 @@
437443
/// # Example
438444
///
439445
/// ```
440-
/// HARNESS_ASSERT_INDEX(0x0001U);
446+
/// HARNESS_ASSERT_INDEX(0x0001);
441447
/// ```
442448
#define HARNESS_ASSERT_INDEX(assert_index) \
443449
do { \

‎harness/tsffs-gcc-arm32.h‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,8 @@
4343
"mov r10, %0; orr r" __tostring(value) ", r" __tostring( \
4444
value) ", r" __tostring(value) \
4545
: \
46-
: "r"(arg0));
46+
: "r"(arg0) \
47+
: "r10");
4748

4849
/// __orr_extended2
4950
///
@@ -61,7 +62,8 @@
6162
"mov r10, %0; mov r9, %1; orr r" __tostring(value) ", r" __tostring( \
6263
value) ", r" __tostring(value) \
6364
: \
64-
: "r"(arg0), "r"(arg1));
65+
: "r"(arg0), "r"(arg1) \
66+
: "r10", "r9");
6567

6668
/// __orr_extended3
6769
///
@@ -80,7 +82,8 @@
8082
"mov r10, %0; mov r9, %1; mov r8, %2; orr r" __tostring( \
8183
value) ", r" __tostring(value) ", r" __tostring(value) \
8284
: \
83-
: "r"(arg0), "r"(arg1), "r"(arg2));
85+
: "r"(arg0), "r"(arg1), "r"(arg2) \
86+
: "r10", "r9", "r8");
8487

8588
/// __orr_extended4
8689
///
@@ -101,7 +104,8 @@
101104
"orr r" __tostring(value) ", r" __tostring(value) ", r" __tostring( \
102105
value) \
103106
: \
104-
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3));
107+
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3) \
108+
: "r10", "r9", "r8", "r7");
105109

106110
/// Magic value defined by SIMICS as the "leaf" value of a CPUID instruction
107111
/// that is treated as a magic instruction.
@@ -285,4 +289,4 @@
285289
__orr_extended1(N_STOP_ASSERT, DEFAULT_INDEX); \
286290
} while (0);
287291

288-
#endif // TSFFS_H
292+
#endif // TSFFS_H

‎harness/tsffs.h‎

Lines changed: 32 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1845,7 +1845,7 @@
18451845
// SPDX-License-Identifier: Apache-2.0
18461846

18471847
/// Definitions and macros for compiled-in harnessing of C and C++ target
1848-
/// software for the RISC-V (32-bit) architecture
1848+
/// software for the aarch64 architecture
18491849

18501850
#ifndef TSFFS_H
18511851
#define TSFFS_H
@@ -1883,10 +1883,11 @@
18831883
/// * `arg0` - The value to place in register `r10`
18841884
#define __orr_extended1(value, arg0) \
18851885
__asm__ __volatile__( \
1886-
"mov x28, %0; orr x" __tostring(value) ", x" __tostring( \
1886+
"mov x10, %0; orr x" __tostring(value) ", x" __tostring( \
18871887
value) ", x" __tostring(value) \
18881888
: \
1889-
: "g"(arg0));
1889+
: "g"((unsigned long long)arg0) \
1890+
: "x10");
18901891

18911892
/// __orr_extended2
18921893
///
@@ -1901,10 +1902,11 @@
19011902
/// * `arg1` - The value to place in register `r9`
19021903
#define __orr_extended2(value, arg0, arg1) \
19031904
__asm__ __volatile__( \
1904-
"mov x28, %0; mov x27, %1; orr x" __tostring(value) ", x" __tostring( \
1905+
"mov x10, %0; mov x9, %1; orr x" __tostring(value) ", x" __tostring( \
19051906
value) ", x" __tostring(value) \
19061907
: \
1907-
: "r"(arg0), "r"(arg1));
1908+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1) \
1909+
: "x10", "x9");
19081910

19091911
/// __orr_extended3
19101912
///
@@ -1918,12 +1920,14 @@
19181920
/// * `arg0` - The value to place in register `r10`
19191921
/// * `arg1` - The value to place in register `r9`
19201922
/// * `arg2` - The value to place in register `r8`
1921-
#define __orr_extended3(value, arg0, arg1, arg2) \
1922-
__asm__ __volatile__( \
1923-
"mov x28, %0; mov x27, %1; mov x26, %2; orr x" __tostring( \
1924-
value) ", x" __tostring(value) ", x" __tostring(value) \
1925-
: \
1926-
: "r"(arg0), "r"(arg1), "r"(arg2));
1923+
#define __orr_extended3(value, arg0, arg1, arg2) \
1924+
__asm__ __volatile__( \
1925+
"mov x10, %0; mov x9, %1; mov x8, %2; orr x" __tostring( \
1926+
value) ", x" __tostring(value) ", x" __tostring(value) \
1927+
: \
1928+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1), \
1929+
"r"((unsigned long long)arg2) \
1930+
: "x10", "x9");
19271931

19281932
/// __orr_extended4
19291933
///
@@ -1940,16 +1944,18 @@
19401944
/// * `arg3` - The value to place in register `r7`
19411945
#define __orr_extended4(value, arg0, arg1, arg2, arg3) \
19421946
__asm__ __volatile__( \
1943-
"mov x28, %0; mov x27, %1; mov x26, %2; mov x25, %3; " \
1947+
"mov x10, %0; mov x9, %1; mov x8, %2; mov x7, %3; " \
19441948
"orr x" __tostring(value) ", x" __tostring(value) ", x" __tostring( \
19451949
value) \
19461950
: \
1947-
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3));
1951+
: "r"((unsigned long long)arg0), "r"((unsigned long long)arg1), \
1952+
"r"((unsigned long long)arg2), "r"((unsigned long long)arg3) \
1953+
: "x10", "x9");
19481954

19491955
/// The default index number used for magic instructions. All magic instructions
19501956
/// support multiple start and stop indices, which defaults to 0 if not
19511957
/// specified.
1952-
#define DEFAULT_INDEX (0x0000U)
1958+
#define DEFAULT_INDEX (0x0000)
19531959

19541960
/// Pseudo-hypercall number to signal the fuzzer to use the first argument to
19551961
/// the magic instruction as the pointer to the testcase buffer and the second
@@ -2021,7 +2027,7 @@
20212027
/// ```
20222028
/// unsigned char buffer[1024];
20232029
/// size_t size;
2024-
/// HARNESS_START_INDEX(0x0001U, buffer, &size);
2030+
/// HARNESS_START_INDEX(0x0001, buffer, &size);
20252031
/// ```
20262032
#define HARNESS_START_INDEX(start_index, buffer, size_ptr) \
20272033
do { \
@@ -2097,7 +2103,7 @@
20972103
///
20982104
/// ```
20992105
/// unsigned char buffer[1024];
2100-
/// HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(0x0001U, buffer, 1024);
2106+
/// HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(0x0001, buffer, 1024);
21012107
/// ```
21022108
#define HARNESS_START_WITH_MAXIMUM_SIZE_INDEX(start_index, buffer, max_size) \
21032109
do { \
@@ -2231,7 +2237,7 @@
22312237
/// # Example
22322238
///
22332239
/// ```
2234-
/// HARNESS_STOP_INDEX(0x0001U);
2240+
/// HARNESS_STOP_INDEX(0x0001);
22352241
/// ```
22362242
#define HARNESS_STOP_INDEX(stop_index) \
22372243
do { \
@@ -2280,7 +2286,7 @@
22802286
/// # Example
22812287
///
22822288
/// ```
2283-
/// HARNESS_ASSERT_INDEX(0x0001U);
2289+
/// HARNESS_ASSERT_INDEX(0x0001);
22842290
/// ```
22852291
#define HARNESS_ASSERT_INDEX(assert_index) \
22862292
do { \
@@ -2334,7 +2340,8 @@
23342340
"mov r10, %0; orr r" __tostring(value) ", r" __tostring( \
23352341
value) ", r" __tostring(value) \
23362342
: \
2337-
: "r"(arg0));
2343+
: "r"(arg0) \
2344+
: "r10");
23382345

23392346
/// __orr_extended2
23402347
///
@@ -2352,7 +2359,8 @@
23522359
"mov r10, %0; mov r9, %1; orr r" __tostring(value) ", r" __tostring( \
23532360
value) ", r" __tostring(value) \
23542361
: \
2355-
: "r"(arg0), "r"(arg1));
2362+
: "r"(arg0), "r"(arg1) \
2363+
: "r10", "r9");
23562364

23572365
/// __orr_extended3
23582366
///
@@ -2371,7 +2379,8 @@
23712379
"mov r10, %0; mov r9, %1; mov r8, %2; orr r" __tostring( \
23722380
value) ", r" __tostring(value) ", r" __tostring(value) \
23732381
: \
2374-
: "r"(arg0), "r"(arg1), "r"(arg2));
2382+
: "r"(arg0), "r"(arg1), "r"(arg2) \
2383+
: "r10", "r9", "r8");
23752384

23762385
/// __orr_extended4
23772386
///
@@ -2392,7 +2401,8 @@
23922401
"orr r" __tostring(value) ", r" __tostring(value) ", r" __tostring( \
23932402
value) \
23942403
: \
2395-
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3));
2404+
: "r"(arg0), "r"(arg1), "r"(arg2), "r"(arg3) \
2405+
: "r10", "r9", "r8", "r7");
23962406

23972407
/// Magic value defined by SIMICS as the "leaf" value of a CPUID instruction
23982408
/// that is treated as a magic instruction.

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