dts: arm64: intel: intel_socfpga: Adding nodes for watchdog

add dts support for watchdog to accomodate watchdog driver bringup on
aglex and agilex5

Signed-off-by: Balsundar Ponnusamy <[email protected]>

Author: pbalsundar

dts/arm64/intel/intel_socfpga_agilex.dtsi

@@ -155,6 +155,33 @@
 				IRQ_DEFAULT_PRIORITY>;
 		reg = <0xffd00100 0x100>;
 		clock-frequency = < 100000000 >;
+	};
+
+	watchdog0: watchdog@ffd00200 {
+		compatible = "snps,designware-watchdog";
+		reg = <0xffd00200 0x100>;
+		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
+		status = "disabled";
+	};
+
+	watchdog1: watchdog@ffd00300 {
+		compatible = "snps,designware-watchdog";
+		reg = <0xffd00300 0x100>;
+		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
+		status = "disabled";
+	};
+
+	watchdog2: watchdog@ffd00400 {
+		compatible = "snps,designware-watchdog";
+		reg = <0xffd00400 0x100>;
+		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
+		status = "disabled";
+	};
+
+	watchdog3: watchdog@ffd00500 {
+		compatible = "snps,designware-watchdog";
+		reg = <0xffd00500 0x100>;
+		clocks = <&clock INTEL_SOCFPGA_CLOCK_WDT>;
 		status = "disabled";
 	};
 };

dts/arm64/intel/intel_socfpga_agilex5.dtsi

@@ -158,6 +158,45 @@
 		reg = <0x10D00100 0x100>;
 		clock-frequency = <100000000>;
 		resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
+	};
+
+	watchdog0: watchdog@10d00200 {
+		compatible = "snps,designware-watchdog";
+		reg = <0x10d00200 0x100>;
+		clock-frequency = <100000000>;
+		resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;
+		status = "disabled";
+	};
+
+	watchdog1: watchdog@10d00300 {
+		compatible = "snps,designware-watchdog";
+		reg = <0x10d00300 0x100>;
+		clock-frequency = <100000000>;
+		resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>;
+		status = "disabled";
+	};
+
+	watchdog2: watchdog@10d00400 {
+		compatible = "snps,designware-watchdog";
+		reg = <0x10d00400 0x100>;
+		clock-frequency = <100000000>;
+		resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>;
+		status = "disabled";
+	};
+
+	watchdog3: watchdog@10d00500 {
+		compatible = "snps,designware-watchdog";
+		reg = <0x10d00500 0x100>;
+		clock-frequency = <100000000>;
+		resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>;
+		status = "disabled";
+	};
+
+	watchdog4: watchdog@10d00600 {
+		compatible = "snps,designware-watchdog";
+		reg = <0x10d00600 0x100>;
+		clock-frequency = <100000000>;
+		resets = <&reset RSTMGR_WATCHDOG4_RSTLINE>;
 		status = "disabled";
 	};