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GroverkssGroverkss
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Integrate llvm-project@7a8090c037255b54895d61df2eb141fee48d6d83 (#20873)
New Revert: llvm/llvm-project#139521 will be fixed in a followup as it is a large change Currently, it carries 4 reverts: - iree-org/llvm-project@13631cf - iree-org/llvm-project@0357fd9 - iree-org/llvm-project@20a9a98 - iree-org/llvm-project@435bb50
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14 files changed

+19
-78
lines changed

14 files changed

+19
-78
lines changed

‎compiler/src/iree/compiler/Codegen/Common/FoldTensorSubsetIntoVectorTransferOps.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ class FoldExtractSliceIntoTransferWrite final
289289
extractSliceOp,
290290
"expect it is not a rank-reduced tensor.extract_slice op");
291291
}
292-
if (!llvm::all_of(extractSliceOp.getMixedOffsets(), isZeroIndex)) {
292+
if (!llvm::all_of(extractSliceOp.getMixedOffsets(), isZeroInteger)) {
293293
return rewriter.notifyMatchFailure(extractSliceOp,
294294
"expect all the offsets are zeros");
295295
}

‎compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -611,8 +611,8 @@ struct ConvertHALInstrumentMemoryLoadOp
611611
(loadSize << 8) | IREE_INSTRUMENT_DISPATCH_TYPE_MEMORY_LOAD));
612612

613613
Value loadPtr = getStridedElementPtr(
614-
loc, llvm::cast<MemRefType>(instrumentOp.getBase().getType()),
615-
operands.getBase(), operands.getIndices(), rewriter);
614+
rewriter, loc, llvm::cast<MemRefType>(instrumentOp.getBase().getType()),
615+
operands.getBase(), operands.getIndices());
616616
Value addressI64 = rewriter.create<LLVM::PtrToIntOp>(loc, i64Type, loadPtr);
617617

618618
appendInstrumentationEntry(loc, instrumentOp.getBuffer(),
@@ -658,8 +658,8 @@ struct ConvertHALInstrumentMemoryStoreOp
658658
(storeSize << 8) | IREE_INSTRUMENT_DISPATCH_TYPE_MEMORY_STORE));
659659

660660
Value storePtr = getStridedElementPtr(
661-
loc, llvm::cast<MemRefType>(instrumentOp.getBase().getType()),
662-
operands.getBase(), operands.getIndices(), rewriter);
661+
rewriter, loc, llvm::cast<MemRefType>(instrumentOp.getBase().getType()),
662+
operands.getBase(), operands.getIndices());
663663
Value addressI64 =
664664
rewriter.create<LLVM::PtrToIntOp>(loc, i64Type, storePtr);
665665

‎compiler/src/iree/compiler/Codegen/LLVMCPU/test/hal_interface_bindings.mlir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ func.func @binding_ptrs() {
2222
// CHECK: %[[OFFSET_PTR0:.+]] = llvm.getelementptr %[[BASE_PTR]][18]
2323
// CHECK: %[[OFFSET_D0:.+]] = llvm.mul %[[C5]], %[[C2]]
2424
// CHECK: %[[INDEX1:.+]] = llvm.add %[[OFFSET_D0]], %[[C1]]
25-
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr %[[OFFSET_PTR0]][%[[INDEX1]]]
25+
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr inbounds|nuw %[[OFFSET_PTR0]][%[[INDEX1]]]
2626
// CHECK: %[[VALUE:.+]] = llvm.load %[[OFFSET_PTR1]]
2727
%c1 = arith.constant 1 : index
2828
%c5 = arith.constant 5 : index
@@ -87,7 +87,7 @@ func.func @binding_ptrs_dynamic() {
8787
// CHECK: %[[INDEX1:.+]] = llvm.mul %[[STRIDE1]], %[[C5]]
8888
// CHECK: %[[T1:.+]] = llvm.add %[[INDEX2]], %[[INDEX1]]
8989
// CHECK: %[[T2:.+]] = llvm.add %[[T1]], %[[C3]]
90-
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr %[[OFFSET_PTR0]][%[[T2]]]
90+
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr inbounds|nuw %[[OFFSET_PTR0]][%[[T2]]]
9191
// CHECK: %[[VALUE:.+]] = llvm.load %[[OFFSET_PTR1]]
9292
%c3 = arith.constant 3 : index
9393
%c5 = arith.constant 5 : index
@@ -130,7 +130,7 @@ func.func @binding_ptrs_sub_byte_dynamic() {
130130
// CHECK: %[[BASE_BIT_OFFSET:.+]] = llvm.mul %[[OFFSET_ZEXT]], %[[C8]]
131131
// CHECK: %[[BASE_OFFSET:.+]] = llvm.udiv %[[BASE_BIT_OFFSET]], %[[C4]]
132132
// CHECK: %[[OFFSET_PTR0:.+]] = llvm.getelementptr %[[BASE_PTR]][%[[BASE_OFFSET]]]
133-
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr %[[OFFSET_PTR0]][7]
133+
// CHECK: %[[OFFSET_PTR1:.+]] = llvm.getelementptr inbounds|nuw %[[OFFSET_PTR0]][7]
134134
// CHECK: %[[VALUE:.+]] = llvm.load %[[OFFSET_PTR1]]
135135
%c7 = arith.constant 7 : index
136136
%value = memref.load %memref[%c7] : memref<?xi4, strided<[1], offset: ?>>

‎compiler/src/iree/compiler/Codegen/LLVMGPU/test/convert_to_nvvm.mlir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ hal.executable @abs_ex_dispatch_0 {
3636
// CHECK-SAME: %[[ARG1:.+]]: !llvm.ptr {llvm.align = 16 : i32, llvm.noalias, llvm.nonnull, llvm.noundef, llvm.readonly},
3737
// CHECK-SAME: %[[ARG2:.+]]: !llvm.ptr {llvm.align = 16 : i32, llvm.noalias, llvm.nonnull, llvm.noundef})
3838
// CHECK: %[[FADD:.+]] = llvm.fadd %{{.*}}, %{{.*}} : f32
39-
// CHECK: %[[ADDR:.+]] = llvm.getelementptr %[[ARG2]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, f32
39+
// CHECK: %[[ADDR:.+]] = llvm.getelementptr inbounds|nuw %[[ARG2]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, f32
4040
// CHECK: llvm.store %[[FADD]], %[[ADDR]] : f32, !llvm.ptr
4141
// -----
4242

@@ -110,14 +110,14 @@ hal.executable @abs_dynamic {
110110
// CHECK-DAG: llvm.intr.assume %[[ARG6_CMP]]
111111
// CHECK-DAG: %[[D2:.+]] = llvm.zext %[[ARG7]] : i32 to i64
112112
// CHECK: %[[GEP1:.+]] = llvm.getelementptr %[[ARG1]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, f32
113-
// CHECK: %[[GEP:.+]] = llvm.getelementptr %[[GEP1]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, f32
113+
// CHECK: %[[GEP:.+]] = llvm.getelementptr inbounds|nuw %[[GEP1]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, f32
114114
// CHECK: %[[LOAD:.+]] = llvm.load %[[GEP]] : !llvm.ptr -> f32
115-
// CHECK: %[[GEP2:.+]] = llvm.getelementptr %[[ARG0]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, i32
115+
// CHECK: %[[GEP2:.+]] = llvm.getelementptr inbounds|nuw %[[ARG0]][%{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr, i32
116116
// CHECK: llvm.load %[[GEP2]] : !llvm.ptr -> i32
117117
// CHECK: %[[FADD:.+]] = llvm.fadd %[[LOAD]], %{{.*}} : f32
118118
// CHECK: %[[ADD:.+]] = llvm.add
119119
// CHECK: %[[ADD2:.+]] = llvm.add
120-
// CHECK: %[[ADDR:.+]] = llvm.getelementptr %[[ARG2]][%[[ADD2]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32
120+
// CHECK: %[[ADDR:.+]] = llvm.getelementptr inbounds|nuw %[[ARG2]][%[[ADD2]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32
121121
// CHECK: llvm.store %[[FADD]], %[[ADDR]] : f32, !llvm.ptr
122122

123123

‎compiler/src/iree/compiler/Codegen/LLVMGPU/test/convert_to_rocdl.mlir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ builtin.module {
3333
// CHECK-SAME: %{{[a-zA-Z0-9]*}}: !llvm.ptr {llvm.align = 16 : i32, llvm.noalias, llvm.nonnull, llvm.noundef},
3434
// CHECK-SAME: %{{[a-zA-Z0-9]*}}: !llvm.ptr {llvm.align = 16 : i32, llvm.noalias, llvm.nonnull, llvm.noundef, llvm.readnone})
3535
// CHECK: rocdl.workgroup.dim.x
36-
// CHECK: llvm.getelementptr %{{.*}} : (!llvm.ptr, i64) -> !llvm.ptr, f32
37-
// INDEX32: llvm.getelementptr %{{.*}} : (!llvm.ptr, i32) -> !llvm.ptr, f32
36+
// CHECK: llvm.getelementptr inbounds|nuw %{{.*}} : (!llvm.ptr, i64) -> !llvm.ptr, f32
37+
// INDEX32: llvm.getelementptr inbounds|nuw %{{.*}} : (!llvm.ptr, i32) -> !llvm.ptr, f32
3838
// CHECK: llvm.fadd
3939

4040

‎compiler/src/iree/compiler/Codegen/Transforms/Transforms.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -956,7 +956,7 @@ struct FoldCollapseShapeIntoInterfaceTensorStoreFullSlice
956956

957957
for (int64_t collapsedDim : collapsedDstDims) {
958958
if (origSizes[collapsedDim] != mixedTensorShape[collapsedDim] ||
959-
!isZeroIndex(origOffsets[collapsedDim])) {
959+
!isZeroInteger(origOffsets[collapsedDim])) {
960960
return rewriter.notifyMatchFailure(
961961
storeOp,
962962
llvm::formatv(

‎compiler/src/iree/compiler/Dialect/Flow/Transforms/ConvertMeshToFlow.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
#include "iree/compiler/Utils/Indexing.h"
1111
#include "iree/compiler/Utils/OpVisitor.h"
1212
#include "iree/compiler/Utils/Permutation.h"
13-
#include "iree/compiler/Utils/SmallVectorDenseMapInfo.h"
13+
#include "llvm/ADT/DenseMapInfo.h"
1414
#include "mlir/Dialect/Affine/IR/AffineOps.h"
1515
#include "mlir/Dialect/Linalg/IR/Linalg.h"
1616
#include "mlir/Dialect/MemRef/Transforms/Transforms.h"

‎compiler/src/iree/compiler/Dialect/LinalgExt/IR/TilingInterfaceImpl.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2514,7 +2514,7 @@ OnlineAttentionOp::generateInitialTensorForPartialReduction(
25142514

25152515
SmallVector<OpFoldResult> tiledShape;
25162516
for (auto [tileSize, dimSize] : llvm::zip_equal(sizes, shape)) {
2517-
if (isZeroIndex(tileSize)) {
2517+
if (isZeroInteger(tileSize)) {
25182518
tiledShape.push_back(dimSize);
25192519
} else {
25202520
tiledShape.push_back(tileSize);
@@ -2914,7 +2914,7 @@ computeCustomOpAllSliceParameters(OpBuilder &builder, Location loc,
29142914
SmallVector<OpFoldResult> tileSizes) {
29152915
assert(ivs.size() == static_cast<size_t>(llvm::count_if(
29162916
llvm::make_range(tileSizes.begin(), tileSizes.end()),
2917-
[](OpFoldResult v) { return !isZeroIndex(v); })) &&
2917+
[](OpFoldResult v) { return !isZeroInteger(v); })) &&
29182918
"expected as many ivs as non-zero sizes");
29192919
unsigned numDims = customOp.getNumLoops();
29202920
unsigned numSymbols = customOp.getNumNonLoopDimensions();

‎compiler/src/iree/compiler/Utils/BUILD.bazel‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,6 @@ iree_compiler_cc_library(
4444
"PassUtils.h",
4545
"PatternUtils.h",
4646
"Permutation.h",
47-
"SmallVectorDenseMapInfo.h",
4847
"StringUtils.h",
4948
"ToolUtils.h",
5049
"TracingUtils.h",

‎compiler/src/iree/compiler/Utils/CMakeLists.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@ iree_cc_library(
2828
"PassUtils.h"
2929
"PatternUtils.h"
3030
"Permutation.h"
31-
"SmallVectorDenseMapInfo.h"
3231
"StringUtils.h"
3332
"ToolUtils.h"
3433
"TracingUtils.h"

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