Integrate llvm-project@bb1f32ded0b7 (#20494)

The changes are caused by:
* llvm/llvm-project#134206

Reverts:
* llvm/llvm-project#125883. This breaks the
RISC-V test: `e2e/math/math_ops_llvm-cpu.mlir`.

---------

Signed-off-by: Jakub Kuderski <[email protected]>

Author: kuhar

compiler/src/iree/compiler/Codegen/Common/FlattenMemRefSubspanPass.cpp

@@ -616,8 +616,8 @@ struct LinearizeTransferWriteIndices final
     }
 
     rewriter.replaceOpWithNewOp<vector::TransferWriteOp>(
-        transferWriteOp, adaptor.getVector(), adaptor.getSource(), linearIndex,
-        AffineMapAttr::get(rewriter.getDimIdentityMap()),
+        transferWriteOp, adaptor.getValueToStore(), adaptor.getSource(),
+        linearIndex, AffineMapAttr::get(rewriter.getDimIdentityMap()),
         transferWriteOp.getInBoundsAttr());
     return success();
   }

compiler/src/iree/compiler/Codegen/Common/GPU/GPUNestedLayoutDistributionPatterns.cpp

@@ -403,7 +403,7 @@ struct DistributeTransferWrite final
                                 DistributionSignature &signature,
                                 PatternRewriter &rewriter) const override {
     NestedLayoutAttr vectorLayout =
-        dyn_cast<NestedLayoutAttr>(signature[writeOp.getVector()]);
+        dyn_cast<NestedLayoutAttr>(signature[writeOp.getValueToStore()]);
     if (!vectorLayout) {
       return rewriter.notifyMatchFailure(writeOp,
                                          "non-nested transfer_write layout");
@@ -439,7 +439,7 @@ struct DistributeTransferWrite final
     }
 
     Value distributedVector =
-        getDistributed(rewriter, writeOp.getVector(), vectorLayout);
+        getDistributed(rewriter, writeOp.getValueToStore(), vectorLayout);
 
     ValueRange indices = writeOp.getIndices();
     AffineMap permMap = writeOp.getPermutationMap();

compiler/src/iree/compiler/Codegen/Common/GPU/VectorReductionToGPU.cpp

@@ -158,7 +158,7 @@ struct InsertToBroadcast final : OpRewritePattern<vector::InsertOp> {
     if (insertOp.getDestVectorType().getNumElements() != 1)
       return failure();
     rewriter.replaceOpWithNewOp<vector::BroadcastOp>(
-        insertOp, insertOp.getDestVectorType(), insertOp.getSource());
+        insertOp, insertOp.getDestVectorType(), insertOp.getValueToStore());
     return success();
   }
 };

compiler/src/iree/compiler/Codegen/Common/HoistUnrolledVectorExtractInsertSlice.cpp

@@ -139,8 +139,10 @@ static scf::ForOp hoistVectorExtractInsertSlice(
   // computed iteratively but whose storage has become loop-invariant.
   NewYieldValuesFn yieldFn = [&](OpBuilder &b, Location loc,
                                  ArrayRef<BlockArgument> newBBArgs) {
-    return llvm::map_to_vector(insertOps,
-                               [](auto v) -> Value { return v.getSource(); });
+    return llvm::map_to_vector(
+        insertOps, [](vector::InsertStridedSliceOp sliceOp) -> Value {
+          return sliceOp.getValueToStore();
+        });
   };
   SmallVector<Value> extractResults = llvm::map_to_vector(
       extractOps, [](auto v) -> Value { return v.getResult(); });
@@ -160,7 +162,7 @@ static scf::ForOp hoistVectorExtractInsertSlice(
   for (auto [idx, insertStridedSliceOp] : llvm::enumerate(insertOps)) {
     insertStridedSliceOp->moveAfter(newForOp);
     rewriter.startOpModification(insertStridedSliceOp);
-    insertStridedSliceOp.getSourceMutable().assign(
+    insertStridedSliceOp.getValueToStoreMutable().assign(
         newForOp.getResults()[initArgNumber + idx + 1]);
     insertStridedSliceOp.getDestMutable().assign(
         newForOp.getResults()[initArgNumber]);

compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtOps.cpp

@@ -5,7 +5,6 @@
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 
 #include "iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtOps.h"
-#include "iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.h"
 #include "mlir/Dialect/Affine/IR/AffineOps.h"
 #include "mlir/Dialect/Utils/IndexingUtils.h"
 #include "mlir/Dialect/Vector/IR/VectorOps.h"
@@ -44,6 +43,8 @@ OpFoldResult ToSIMTOp::fold(FoldAdaptor) {
 // TransferGatherOp
 //===----------------------------------------------------------------------===//
 
+VectorType TransferGatherOp::getVectorType() { return getType(); }
+
 Speculation::Speculatability TransferGatherOp::getSpeculatability() {
   if (isa<RankedTensorType>(getSource().getType())) {
     return Speculation::Speculatable;
@@ -143,7 +144,7 @@ void TransferGatherOp::print(OpAsmPrinter &p) {
   p << " : ";
   p << getShapedType() << ", ";
   llvm::interleaveComma(getIndexVecs().getType(), p);
-  p << ", " << getVectorType();
+  p << ", " << getType();
 }
 
 static LogicalResult
@@ -263,7 +264,7 @@ static LogicalResult verifyPermutationMap(
 LogicalResult TransferGatherOp::verify() {
   // Consistency of elemental types in source and vector.
   ShapedType shapedType = getShapedType();
-  VectorType vectorType = getVectorType();
+  VectorType vectorType = getType();
   VectorType maskType = getMaskType();
   Type paddingType = getPadding().getType();
   AffineMap permutationMap = getPermutationMap();
@@ -642,7 +643,7 @@ struct FoldContigousGatherToTransferRead final
 
     // Canonicalize to vector.transfer_read.
     rewriter.replaceOpWithNewOp<vector::TransferReadOp>(
-        xferOp, xferOp.getVectorType(), xferOp.getSource(), xferOp.getIndices(),
+        xferOp, xferOp.getType(), xferOp.getSource(), xferOp.getIndices(),
         xferOp.getPermutationMap(), xferOp.getPadding(), xferOp.getMask(),
         xferOp.getInBounds());
     return success();

compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtOps.td

@@ -119,17 +119,17 @@ def IREEVectorExt_TransferGatherOp : IREEVectorExt_PureOp<"transfer_gather", [
     DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
     DeclareOpInterfaceMethods<ConditionallySpeculatable>,
     AttrSizedOperandSegments
-  ]>,
-  Arguments<(ins AnyShaped:$source,
-                 Variadic<Index>:$indices,
-                 Variadic<VectorOfAnyRankOf<[Index]>>:$index_vecs,
-                 BoolArrayAttr:$indexed,
-                 AffineMapArrayAttr:$indexed_maps,
-                 AffineMapAttr:$permutation_map,
-                 AnyType:$padding,
-                 Optional<VectorOfNonZeroRankOf<[I1]>>:$mask,
-                 BoolArrayAttr:$in_bounds)>,
-  Results<(outs AnyVectorOfAnyRank:$vector)> {
+  ]> {
+  let arguments = (ins AnyShaped:$source,
+                       Variadic<Index>:$indices,
+                       Variadic<VectorOfAnyRankOf<[Index]>>:$index_vecs,
+                       BoolArrayAttr:$indexed,
+                       AffineMapArrayAttr:$indexed_maps,
+                       AffineMapAttr:$permutation_map,
+                       AnyType:$padding,
+                       Optional<VectorOfNonZeroRankOf<[I1]>>:$mask,
+                       BoolArrayAttr:$in_bounds);
+  let results = (outs AnyVectorOfAnyRank:$vector);
 
   let summary = "Gathers a supervector from memory into an SSA vector value.";
 

compiler/src/iree/compiler/Codegen/SPIRV/SPIRVInitialVectorLowering.cpp

@@ -103,9 +103,11 @@ Operation *stripElementBitPatternPreservingParents(Value op) {
             .Case<vector::ExtractOp, vector::ExtractElementOp,
                   vector::ExtractStridedSliceOp>(
                 [](auto extract) { return extract.getVector(); })
-            .Case<vector::InsertOp, vector::InsertElementOp,
-                  vector::InsertStridedSliceOp>(
-                [](auto insert) { return insert.getSource(); })
+            .Case<vector::InsertElementOp>([](vector::InsertElementOp insert) {
+              return insert.getSource();
+            })
+            .Case<vector::InsertOp, vector::InsertStridedSliceOp>(
+                [](auto insert) { return insert.getValueToStore(); })
             .Case<vector::TransposeOp>([](vector::TransposeOp transpose) {
               return transpose.getVector();
             })

compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorizeLoadStore.cpp

@@ -475,8 +475,8 @@ class ProcessTransferWrite final
     // If the transfer_write can be replaced by a store after vectorization cast
     // the original value and use StoreOp.
     if (*vectorMemrefElemSize == *writeVecSize) {
-      Value data = rewriter.create<vector::BitCastOp>(loc, memrefVectorType,
-                                                      adaptor.getVector());
+      Value data = rewriter.create<vector::BitCastOp>(
+          loc, memrefVectorType, adaptor.getValueToStore());
       rewriter.replaceOpWithNewOp<memref::StoreOp>(
           write, data, adaptor.getSource(), indices.value());
       return success();
@@ -506,7 +506,7 @@ class ProcessTransferWrite final
     for (int i = 0; i < vectorCount; ++i) {
       offsets.back() = i * memrefVectorType.getNumElements();
       auto slice = rewriter.create<vector::ExtractStridedSliceOp>(
-          loc, adaptor.getVector(), offsets, sizes, strides);
+          loc, adaptor.getValueToStore(), offsets, sizes, strides);
       auto component =
           rewriter.create<vector::BitCastOp>(loc, memrefVectorType, slice);
       Value iVal = rewriter.create<arith::ConstantIndexOp>(loc, i);