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MaheshRavishankarMaheshRavishankar
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Revert "[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (llvm#119461)"
This reverts commit 169c32e.
1 parent 3f1486f commit 3785531

35 files changed

+267
-176
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
105105
static cl::opt<bool>
106106
EnableVLOptimizer("riscv-enable-vl-optimizer",
107107
cl::desc("Enable the RISC-V VL Optimizer pass"),
108-
cl::init(true), cl::Hidden);
108+
cl::init(false), cl::Hidden);
109109

110110
static cl::opt<bool> DisableVectorMaskMutation(
111111
"riscv-disable-vector-mask-mutation",

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,6 @@
119119
; RV64-NEXT: RISC-V Optimize W Instructions
120120
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
121121
; CHECK-NEXT: RISC-V Merge Base Offset
122-
; CHECK-NEXT: MachineDominator Tree Construction
123-
; CHECK-NEXT: RISC-V VL Optimizer
124122
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
125123
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
126124
; CHECK-NEXT: RISC-V Landing Pad Setup
@@ -131,6 +129,7 @@
131129
; CHECK-NEXT: Live Variable Analysis
132130
; CHECK-NEXT: Eliminate PHI nodes for register allocation
133131
; CHECK-NEXT: Two-Address instruction pass
132+
; CHECK-NEXT: MachineDominator Tree Construction
134133
; CHECK-NEXT: Slot index numbering
135134
; CHECK-NEXT: Live Interval Analysis
136135
; CHECK-NEXT: Register Coalescer

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2654,8 +2654,9 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26542654
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
26552655
; CHECK: # %bb.0:
26562656
; CHECK-NEXT: li a1, 511
2657-
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2657+
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
26582658
; CHECK-NEXT: vxor.vx v8, v8, a1
2659+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
26592660
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
26602661
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
26612662
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -2669,8 +2670,9 @@ define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26692670
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
26702671
; CHECK-ZVBB: # %bb.0:
26712672
; CHECK-ZVBB-NEXT: li a1, 511
2672-
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2673+
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
26732674
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
2675+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
26742676
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
26752677
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
26762678
; CHECK-ZVBB-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,9 @@ define void @abs_v6i16(ptr %x) {
3939
; CHECK: # %bb.0:
4040
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4141
; CHECK-NEXT: vle16.v v8, (a0)
42+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4243
; CHECK-NEXT: vrsub.vi v9, v8, 0
44+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4345
; CHECK-NEXT: vmax.vv v8, v8, v9
4446
; CHECK-NEXT: vse16.v v8, (a0)
4547
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -784,9 +784,11 @@ define void @copysign_v6bf16(ptr %x, ptr %y) {
784784
; CHECK-NEXT: vle16.v v8, (a1)
785785
; CHECK-NEXT: vle16.v v9, (a0)
786786
; CHECK-NEXT: lui a1, 8
787+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
787788
; CHECK-NEXT: vand.vx v8, v8, a1
788789
; CHECK-NEXT: addi a1, a1, -1
789790
; CHECK-NEXT: vand.vx v9, v9, a1
791+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
790792
; CHECK-NEXT: vor.vv v8, v9, v8
791793
; CHECK-NEXT: vse16.v v8, (a0)
792794
; CHECK-NEXT: ret
@@ -842,9 +844,11 @@ define void @copysign_v6f16(ptr %x, ptr %y) {
842844
; ZVFHMIN-NEXT: vle16.v v8, (a1)
843845
; ZVFHMIN-NEXT: vle16.v v9, (a0)
844846
; ZVFHMIN-NEXT: lui a1, 8
847+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
845848
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
846849
; ZVFHMIN-NEXT: addi a1, a1, -1
847850
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
851+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
848852
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
849853
; ZVFHMIN-NEXT: vse16.v v8, (a0)
850854
; ZVFHMIN-NEXT: ret
@@ -916,10 +920,12 @@ define void @copysign_vf_v6bf16(ptr %x, bfloat %y) {
916920
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
917921
; CHECK-NEXT: vle16.v v8, (a0)
918922
; CHECK-NEXT: lui a2, 8
923+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
919924
; CHECK-NEXT: vmv.v.x v9, a1
920925
; CHECK-NEXT: addi a1, a2, -1
921926
; CHECK-NEXT: vand.vx v8, v8, a1
922927
; CHECK-NEXT: vand.vx v9, v9, a2
928+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
923929
; CHECK-NEXT: vor.vv v8, v8, v9
924930
; CHECK-NEXT: vse16.v v8, (a0)
925931
; CHECK-NEXT: ret
@@ -976,10 +982,12 @@ define void @copysign_vf_v6f16(ptr %x, half %y) {
976982
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
977983
; ZVFHMIN-NEXT: vle16.v v8, (a0)
978984
; ZVFHMIN-NEXT: lui a2, 8
985+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
979986
; ZVFHMIN-NEXT: vmv.v.x v9, a1
980987
; ZVFHMIN-NEXT: addi a1, a2, -1
981988
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
982989
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
990+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
983991
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
984992
; ZVFHMIN-NEXT: vse16.v v8, (a0)
985993
; ZVFHMIN-NEXT: ret
@@ -1053,9 +1061,11 @@ define void @copysign_neg_v6bf16(ptr %x, ptr %y) {
10531061
; CHECK-NEXT: vle16.v v9, (a0)
10541062
; CHECK-NEXT: lui a1, 8
10551063
; CHECK-NEXT: addi a2, a1, -1
1064+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
10561065
; CHECK-NEXT: vxor.vx v8, v8, a1
10571066
; CHECK-NEXT: vand.vx v9, v9, a2
10581067
; CHECK-NEXT: vand.vx v8, v8, a1
1068+
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
10591069
; CHECK-NEXT: vor.vv v8, v9, v8
10601070
; CHECK-NEXT: vse16.v v8, (a0)
10611071
; CHECK-NEXT: ret
@@ -1115,9 +1125,11 @@ define void @copysign_neg_v6f16(ptr %x, ptr %y) {
11151125
; ZVFHMIN-NEXT: vle16.v v9, (a0)
11161126
; ZVFHMIN-NEXT: lui a1, 8
11171127
; ZVFHMIN-NEXT: addi a2, a1, -1
1128+
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11181129
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
11191130
; ZVFHMIN-NEXT: vand.vx v9, v9, a2
11201131
; ZVFHMIN-NEXT: vand.vx v8, v8, a1
1132+
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
11211133
; ZVFHMIN-NEXT: vor.vv v8, v9, v8
11221134
; ZVFHMIN-NEXT: vse16.v v8, (a0)
11231135
; ZVFHMIN-NEXT: ret
@@ -1195,12 +1207,12 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
11951207
; CHECK-NEXT: vle32.v v9, (a1)
11961208
; CHECK-NEXT: lui a1, 8
11971209
; CHECK-NEXT: addi a2, a1, -1
1198-
; CHECK-NEXT: vand.vx v8, v8, a2
11991210
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
1211+
; CHECK-NEXT: vand.vx v8, v8, a2
12001212
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
1201-
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12021213
; CHECK-NEXT: vxor.vx v9, v10, a1
12031214
; CHECK-NEXT: vand.vx v9, v9, a1
1215+
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12041216
; CHECK-NEXT: vor.vv v8, v8, v9
12051217
; CHECK-NEXT: vse16.v v8, (a0)
12061218
; CHECK-NEXT: ret
@@ -1265,10 +1277,12 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
12651277
; ZVFHMIN-NEXT: vle32.v v9, (a1)
12661278
; ZVFHMIN-NEXT: lui a1, 8
12671279
; ZVFHMIN-NEXT: addi a2, a1, -1
1280+
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12681281
; ZVFHMIN-NEXT: vand.vx v8, v8, a2
12691282
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
12701283
; ZVFHMIN-NEXT: vxor.vx v9, v10, a1
12711284
; ZVFHMIN-NEXT: vand.vx v9, v9, a1
1285+
; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12721286
; ZVFHMIN-NEXT: vor.vv v8, v8, v9
12731287
; ZVFHMIN-NEXT: vse16.v v8, (a0)
12741288
; ZVFHMIN-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -909,9 +909,8 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() {
909909
define <16 x i8> @buildvec_not_vid_v16i8() {
910910
; CHECK-LABEL: buildvec_not_vid_v16i8:
911911
; CHECK: # %bb.0:
912-
; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma
913-
; CHECK-NEXT: vmv.v.i v9, 3
914912
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
913+
; CHECK-NEXT: vmv.v.i v9, 3
915914
; CHECK-NEXT: vmv.v.i v8, 0
916915
; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma
917916
; CHECK-NEXT: vslideup.vi v8, v9, 6

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -348,9 +348,8 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
348348
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
349349
; CHECK-LABEL: splat_ve4_ins_i1ve3:
350350
; CHECK: # %bb.0:
351-
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, ma
352-
; CHECK-NEXT: vmv.v.i v9, 3
353351
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
352+
; CHECK-NEXT: vmv.v.i v9, 3
354353
; CHECK-NEXT: vmv.v.i v10, 4
355354
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
356355
; CHECK-NEXT: vslideup.vi v10, v9, 1
@@ -433,9 +432,8 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
433432
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
434433
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
435434
; CHECK: # %bb.0:
436-
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, ma
437-
; CHECK-NEXT: vmv.v.i v10, 4
438435
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
436+
; CHECK-NEXT: vmv.v.i v10, 4
439437
; CHECK-NEXT: vmv.v.i v11, 0
440438
; CHECK-NEXT: li a0, 70
441439
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,17 +1100,15 @@ define void @mulhu_v8i16(ptr %x) {
11001100
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11011101
; CHECK-NEXT: vle16.v v8, (a0)
11021102
; CHECK-NEXT: vmv.v.i v9, 0
1103-
; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
11041103
; CHECK-NEXT: vmv.v.i v10, 1
11051104
; CHECK-NEXT: li a1, 33
11061105
; CHECK-NEXT: vmv.s.x v0, a1
11071106
; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
11081107
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
1109-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
11101108
; CHECK-NEXT: vmv.v.i v11, 3
11111109
; CHECK-NEXT: vle16.v v12, (a1)
11121110
; CHECK-NEXT: vmerge.vim v11, v11, 2, v0
1113-
; CHECK-NEXT: vmv1r.v v13, v9
1111+
; CHECK-NEXT: vmv.v.i v13, 0
11141112
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
11151113
; CHECK-NEXT: vslideup.vi v9, v10, 6
11161114
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,9 +97,8 @@ define <4 x i32> @v4i32_v8i32(<8 x i32>) {
9797
define <4 x i32> @v4i32_v16i32(<16 x i32>) {
9898
; RV32-LABEL: v4i32_v16i32:
9999
; RV32: # %bb.0:
100-
; RV32-NEXT: vsetivli zero, 2, e16, m1, ta, ma
101-
; RV32-NEXT: vmv.v.i v12, 1
102100
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
101+
; RV32-NEXT: vmv.v.i v12, 1
103102
; RV32-NEXT: vmv.v.i v14, 6
104103
; RV32-NEXT: li a0, 32
105104
; RV32-NEXT: vmv.v.i v0, 10

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