Skip to content

Commit 9c858f5

Browse files
SisyphSisyph
authored
[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (llvm#157516)
These can be represented by the same definition. It is just a RegisterOperand wrapper for a VGPR register class with a DecoderMethod override. NFC.
1 parent a6af641 commit 9c858f5

File tree

6 files changed

+59
-55
lines changed

6 files changed

+59
-55
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1898,7 +1898,7 @@ class getVregSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 1> {
18981898
!eq(VT.Size, 64) : RegisterOperand<VReg_64>,
18991899
!eq(VT.Size, 48) : RegisterOperand<VReg_64>,
19001900
!eq(VT.Size, 16) : !if(IsTrue16,
1901-
!if(IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
1901+
!if(IsFake16, VGPROp_32_Lo128, VGPROp_16_Lo128),
19021902
RegisterOperand<VGPR_32>),
19031903
1 : RegisterOperand<VGPR_32>);
19041904
}
@@ -1950,6 +1950,20 @@ class getVOP3VRegSrcForVT<ValueType VT> {
19501950
1 : VRegSrc_32);
19511951
}
19521952

1953+
// VGPR only VOP3 src with 8 bit encoding e.g. VOP3DPP src0.
1954+
class getVGPRSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
1955+
RegisterOperand ret =
1956+
!cond(!eq(VT.Size, 128) : VGPROp_128,
1957+
!eq(VT.Size, 96) : VGPROp_96,
1958+
!eq(VT.Size, 64) : VGPROp_64,
1959+
!eq(VT.Size, 48) : VGPROp_64,
1960+
!eq(VT.Size, 16) : !if(IsTrue16,
1961+
!if(IsFake16, VGPROp_32,
1962+
VGPROp_16),
1963+
VGPROp_32),
1964+
1 : VGPROp_32);
1965+
}
1966+
19531967
// Src2 of VOP3 DPP instructions cannot be a literal
19541968
class getVOP3DPPSrcForVT<ValueType VT, bit IsFake16 = 1> {
19551969
RegisterOperand ret =
@@ -2671,7 +2685,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
26712685
field RegisterOperand Src0DPP = getVregSrcForVT<Src0VT>.ret;
26722686
field RegisterOperand Src1DPP = getVregSrcForVT<Src1VT>.ret;
26732687
field RegisterOperand Src2DPP = getVregSrcForVT<Src2VT>.ret;
2674-
field RegisterOperand Src0VOP3DPP = VGPRSrc_32;
2688+
field RegisterOperand Src0VOP3DPP = getVGPRSrcForVT<Src0VT>.ret;
26752689
field RegisterOperand Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT>.ret;
26762690
field RegisterOperand Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT>.ret;
26772691
field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
@@ -2887,7 +2901,7 @@ class VOPProfile_True16<VOPProfile P> : VOPProfile<P.ArgVT> {
28872901
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0 /*IsFake16*/>.ret;
28882902
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0 /*IsFake16*/>.ret;
28892903
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0 /*IsFake16*/>.ret;
2890-
let Src0VOP3DPP = !if (!eq(Src0VT.Size, 16), VGPRSrc_16, VGPRSrc_32);
2904+
let Src0VOP3DPP = !if (!eq(Src0VT.Size, 16), VGPROp_16, VGPROp_32);
28912905
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0 /*IsFake16*/>.ret;
28922906
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0 /*IsFake16*/>.ret;
28932907
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 19 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1307,51 +1307,41 @@ def VRegSrc_fake16: SrcReg9<VGPR_32> {
13071307
let EncoderMethod = "getMachineOpValueT16";
13081308
}
13091309
//===----------------------------------------------------------------------===//
1310-
// VGPRSrc_*
1310+
// VGPROp_* An 8-bit RegisterOperand wrapper for a VGPR
13111311
//===----------------------------------------------------------------------===//
13121312

1313-
// An 8-bit RegisterOperand wrapper for a VGPR
1314-
def VGPRSrc_32 : RegisterOperand<VGPR_32> {
1315-
let DecoderMethod = "DecodeVGPR_32RegisterClass";
1313+
class VGPROp<RegisterClass regClass> : RegisterOperand<regClass> {
1314+
let DecoderMethod = "Decode" # regClass # "RegisterClass";
13161315
}
1317-
def VGPRSrc_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {
1318-
let DecoderMethod = "DecodeVGPR_32RegisterClass";
1316+
class VGPROp_Align2<RegisterClass regClass> : RegisterOperand<!cast<RegisterClass>(regClass#_Align2)> {
1317+
let DecoderMethod = "Decode" # regClass # "RegisterClass";
13191318
}
1320-
def VGPRSrc_64 : RegisterOperand<VReg_64> {
1321-
let DecoderMethod = "DecodeVReg_64RegisterClass";
1319+
multiclass VGPROp_Aligned<RegisterClass regClass> {
1320+
def _Align1 : VGPROp<regClass>;
1321+
def _Align2 : VGPROp_Align2<regClass>;
13221322
}
13231323

1324-
def VGPRSrc_96 : RegisterOperand<VReg_96> {
1325-
let DecoderMethod = "DecodeVReg_96RegisterClass";
1324+
// TODO: These cases should use default target alignment
1325+
def VGPROp_16 : VGPROp<VGPR_16> {
1326+
let EncoderMethod = "getMachineOpValueT16";
13261327
}
1328+
def VGPROp_32 : VGPROp<VGPR_32>;
13271329

1328-
def VGPRSrc_128 : RegisterOperand<VReg_128> {
1329-
let DecoderMethod = "DecodeVReg_128RegisterClass";
1330+
foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "512", "1024"] in {
1331+
def VGPROp_#size : VGPROp<!cast<RegisterClass>("VReg_"#size)>;
13301332
}
13311333

1332-
def VGPRSrc_192 : RegisterOperand<VReg_192> {
1333-
let DecoderMethod = "DecodeVReg_192RegisterClass";
1334+
foreach size = ["64", "96", "128", "160", "256", "1024"] in {
1335+
defm VGPROp_#size : VGPROp_Aligned<!cast<RegisterClass>("VReg_"#size)>;
13341336
}
13351337

1336-
def VGPRSrc_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {
1338+
def VGPROp_16_Lo128 : RegisterOperand<VGPR_16_Lo128> {
13371339
let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
13381340
let EncoderMethod = "getMachineOpValueT16Lo128";
13391341
}
13401342

1341-
// True 16 operands.
1342-
def VGPRSrc_16 : RegisterOperand<VGPR_16> {
1343-
let DecoderMethod = "DecodeVGPR_16RegisterClass";
1344-
let EncoderMethod = "getMachineOpValueT16";
1345-
}
1346-
1347-
// TODO: These cases should use default target alignment
1348-
def VGPROp_16 : RegisterOperand<VGPR_16>;
1349-
def VGPROp_32 : RegisterOperand<VGPR_32>;
1350-
1351-
foreach size = ["64", "96", "128", "160", "256", "1024" ] in {
1352-
def VGPROp_#size : RegisterOperand<!cast<RegisterClass>("VReg_"#size)>;
1353-
def VGPROp_#size#_Align1 : RegisterOperand<!cast<RegisterClass>("VReg_"#size)>;
1354-
def VGPROp_#size#_Align2 : RegisterOperand<!cast<RegisterClass>("VReg_"#size#_Align2)>;
1343+
def VGPROp_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {
1344+
let DecoderMethod = "DecodeVGPR_32RegisterClass";
13551345
}
13561346

13571347
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -416,12 +416,12 @@ def VOP_MADAK_F16_t16 : VOP_MADAK <f16> {
416416
let IsTrue16 = 1;
417417
let IsRealTrue16 = 1;
418418
let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
419-
let Ins32 = (ins VSrcT_f16_Lo128:$src0, VGPRSrc_16_Lo128:$src1, ImmOpType:$imm);
419+
let Ins32 = (ins VSrcT_f16_Lo128:$src0, VGPROp_16_Lo128:$src1, ImmOpType:$imm);
420420
}
421421
def VOP_MADAK_F16_fake16 : VOP_MADAK <f16> {
422422
let IsTrue16 = 1;
423423
let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
424-
let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, VGPRSrc_32_Lo128:$src1, ImmOpType:$imm);
424+
let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, VGPROp_32_Lo128:$src1, ImmOpType:$imm);
425425
}
426426
def VOP_MADAK_F32 : VOP_MADAK <f32>;
427427
def VOP_MADAK_F64 : VOP_MADAK <f64>;
@@ -452,12 +452,12 @@ def VOP_MADMK_F16_t16 : VOP_MADMK <f16> {
452452
let IsTrue16 = 1;
453453
let IsRealTrue16 = 1;
454454
let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
455-
let Ins32 = (ins VSrcT_f16_Lo128:$src0, ImmOpType:$imm, VGPRSrc_16_Lo128:$src1);
455+
let Ins32 = (ins VSrcT_f16_Lo128:$src0, ImmOpType:$imm, VGPROp_16_Lo128:$src1);
456456
}
457457
def VOP_MADMK_F16_fake16 : VOP_MADMK <f16> {
458458
let IsTrue16 = 1;
459459
let DstRC = getVALUDstForVT_fake16<DstVT>.ret;
460-
let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, ImmOpType:$imm, VGPRSrc_32_Lo128:$src1);
460+
let Ins32 = (ins VSrcFake16_f16_Lo128:$src0, ImmOpType:$imm, VGPROp_32_Lo128:$src1);
461461
}
462462
def VOP_MADMK_F32 : VOP_MADMK <f32>;
463463
def VOP_MADMK_F64 : VOP_MADMK <f64>;
@@ -496,14 +496,14 @@ class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, v
496496
HasClamp, HasModifiers, HasModifiers, HasOMod,
497497
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2Mod, HasOpSel>.ret;
498498
// We need a dummy src2 tied to dst to track the use of that register for s_delay_alu
499-
let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPRSrc_32:$src2X);
500-
let InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y, VGPRSrc_32:$src2Y);
499+
let InsVOPDX = (ins Src0RC32:$src0X, Src1RC32:$vsrc1X, VGPROp_32:$src2X);
500+
let InsVOPDY = (ins Src0RC32:$src0Y, Src1RC32:$vsrc1Y, VGPROp_32:$src2Y);
501501
let InsVOPD3X = (ins Src0ModVOPD3:$src0X_modifiers, Src0VOPD3:$src0X,
502502
Src1ModVOPD3:$vsrc1X_modifiers, Src1RC32:$vsrc1X,
503-
VGPRSrc_32:$src2X);
503+
VGPROp_32:$src2X);
504504
let InsVOPD3Y = (ins Src0ModVOPD3:$src0Y_modifiers, Src0VOPD3:$src0Y,
505505
Src1ModVOPD3:$vsrc1Y_modifiers, Src1RC32:$vsrc1Y,
506-
VGPRSrc_32:$src2Y);
506+
VGPROp_32:$src2Y);
507507

508508
let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
509509
Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
@@ -565,7 +565,7 @@ def VOP_MAC_F16_t16 : VOP_MAC <f16> {
565565
let DstRC64 = getVALUDstForVT<DstVT, 1/*IsTrue*/, 1/*IsVOP3Encoding*/>.ret;
566566
let Src0RC64 = getVOP3SrcForVT<Src0VT, 1/*IsTrue16*/>.ret;
567567
let Src1RC64 = getVOP3SrcForVT<Src1VT, 1/*IsTrue16*/>.ret;
568-
let Src0VOP3DPP = VGPRSrc_16;
568+
let Src0VOP3DPP = VGPROp_16;
569569
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
570570
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
571571
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
@@ -597,7 +597,7 @@ def VOP_MAC_F16_fake16 : VOP_MAC <f16> {
597597
getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret:$src2, // stub argument
598598
dpp8:$dpp8, Dpp8FI:$fi);
599599
let DstRC64 = getVALUDstForVT<DstVT>.ret;
600-
let Src0VOP3DPP = VGPRSrc_32;
600+
let Src0VOP3DPP = VGPROp_32;
601601
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
602602
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
603603
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 1/*IsFake16*/>.ret;
@@ -796,7 +796,7 @@ def VOP2e_I16_I16_I16_I1_true16 : VOP2e_SGPR<[i16, i16, i16, i1]> {
796796
Src2RC64, NumSrcArgs,
797797
HasClamp, 1/*HasModifiers*/, 0/*HasSrc2Mods*/, HasOMod,
798798
Src0Mod, Src1Mod, Src2Mod, 1/*HasOpSel*/>.ret;
799-
let Src0VOP3DPP = VGPRSrc_16;
799+
let Src0VOP3DPP = VGPROp_16;
800800
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
801801
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<f16, DstVT, 0/*IsFake16*/>.ret;
802802
let Src1ModVOP3DPP = getSrcModVOP3VC<f16, 0/*IsFake16*/>.ret;
@@ -808,7 +808,7 @@ def VOP2e_I16_I16_I16_I1_fake16 : VOP2e_SGPR<[i16, i16, i16, i1]> {
808808
let Src0Mod = getSrc0Mod<f16, DstVT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
809809
let Src1Mod = getSrcMod<f16, 1/*IsTrue16*/, 1/*IsFake16*/>.ret;
810810

811-
let Src0VOP3DPP = VGPRSrc_32;
811+
let Src0VOP3DPP = VGPROp_32;
812812
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
813813
let Src0ModVOP3DPP = getSrc0ModVOP3DPP<f16, DstVT, 1/*IsFake16*/>.ret;
814814
let Src1ModVOP3DPP = getSrcModVOP3VC<f16, 1/*IsFake16*/>.ret;

‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class VOP3P_Mix_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR,
4444
FP16InputMods:$src1_modifiers, Src1RC:$src1,
4545
FP16InputMods:$src2_modifiers, Src2RC:$src2);
4646
dag dpp_srcs =
47-
(ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0,
47+
(ins FPVRegInputMods:$src0_modifiers, VGPROp_32:$src0,
4848
FPVRegInputMods:$src1_modifiers, VRegSrc_32:$src1,
4949
FP16InputMods:$src2_modifiers, Src2RC:$src2);
5050

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType
100100
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
101101
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
102102
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
103-
let Src0VOP3DPP = VGPRSrc_16;
103+
let Src0VOP3DPP = VGPROp_16;
104104
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
105105
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
106106

@@ -126,7 +126,7 @@ multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType
126126
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
127127
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
128128
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
129-
let Src0VOP3DPP = VGPRSrc_32;
129+
let Src0VOP3DPP = VGPROp_32;
130130
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
131131
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
132132

@@ -173,7 +173,7 @@ multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, Va
173173
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
174174
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
175175
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
176-
let Src0VOP3DPP = VGPRSrc_16;
176+
let Src0VOP3DPP = VGPROp_16;
177177
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
178178
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
179179

@@ -197,7 +197,7 @@ multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, Va
197197
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
198198
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
199199
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
200-
let Src0VOP3DPP = VGPRSrc_32;
200+
let Src0VOP3DPP = VGPROp_32;
201201
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
202202
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
203203

@@ -892,7 +892,7 @@ class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType
892892
// DPP8 forbids modifiers and can inherit from VOPC_Profile
893893

894894
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
895-
dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VCSrc_b32:$src1);
895+
dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPROp_32:$src0, VCSrc_b32:$src1);
896896
let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
897897
(ins)));
898898
let AsmVOP3Base = "$sdst, $src0_modifiers, $src1";
@@ -915,7 +915,7 @@ multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
915915
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
916916
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
917917
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
918-
let Src0VOP3DPP = VGPRSrc_16;
918+
let Src0VOP3DPP = VGPROp_16;
919919
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
920920
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
921921

@@ -941,7 +941,7 @@ multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> {
941941
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
942942
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
943943
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
944-
let Src0VOP3DPP = VGPRSrc_32;
944+
let Src0VOP3DPP = VGPROp_32;
945945
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
946946
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
947947

@@ -985,7 +985,7 @@ multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
985985
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
986986
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
987987
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
988-
let Src0VOP3DPP = VGPRSrc_16;
988+
let Src0VOP3DPP = VGPROp_16;
989989
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
990990
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
991991

@@ -1009,7 +1009,7 @@ multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> {
10091009
let Src0ModDPP = getSrcModDPP_t16<Src0VT, 1/*IsFake16*/>.ret;
10101010
let Src1ModDPP = getSrcModDPP_t16<Src1VT, 1/*IsFake16*/>.ret;
10111011
let Src2ModDPP = getSrcModDPP_t16<Src2VT, 1/*IsFake16*/>.ret;
1012-
let Src0VOP3DPP = VGPRSrc_32;
1012+
let Src0VOP3DPP = VGPROp_32;
10131013
let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 1/*IsFake16*/>.ret;
10141014
let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 1/*IsFake16*/>.ret;
10151015

‎llvm/lib/Target/AMDGPU/VOPDInstructions.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,7 @@ foreach Gen = [GFX11GenD, GFX12GenD, GFX1250GenD] in {
224224
defvar isOpXMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"));
225225
defvar isOpYMADK = !or(!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
226226
defvar OpName = "V_DUAL_" # !substr(x,2) # "_X_" # !substr(y,2) # Gen.Suffix;
227-
defvar outs = (outs VGPRSrc_32:$vdstX, VOPDDstYOperand:$vdstY);
227+
defvar outs = (outs VGPROp_32:$vdstX, VOPDDstYOperand:$vdstY);
228228
if !or(isOpXMADK, isOpYMADK) then {
229229
// If Both X and Y are MADK, the mandatory literal of X additionally must
230230
// use an alternate operand format which defers to the 'real' Y literal.

0 commit comments

Comments
 (0)