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[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (llvm#115200)
For GFX10+, currently null cannot be used as dst reg in instructions that expect the dst reg to be 128b or larger (e.g., s_load_dwordx4). This patch fixes this problem while ensuring null cannot be used as S#, T#, or V#.
1 parent 9d8e634 commit b2adeae

26 files changed

+1485
-76
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9760,10 +9760,14 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
97609760
case MCK_SReg_64:
97619761
case MCK_SReg_64_XEXEC:
97629762
// Null is defined as a 32-bit register but
9763-
// it should also be enabled with 64-bit operands.
9764-
// The following code enables it for SReg_64 operands
9763+
// it should also be enabled with 64-bit operands or larger.
9764+
// The following code enables it for SReg_64 and larger operands
97659765
// used as source and destination. Remaining source
97669766
// operands are handled in isInlinableImm.
9767+
case MCK_SReg_96:
9768+
case MCK_SReg_128:
9769+
case MCK_SReg_256:
9770+
case MCK_SReg_512:
97679771
return Operand.isNull() ? Match_Success : Match_InvalidOperand;
97689772
default:
97699773
return Match_InvalidOperand;

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
168168
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset),
169169
(ins SCSrc_b32:$soffset));
170170

171-
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset,
171+
dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset,
172172
(ins Offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
173173

174174
dag Inputs = !if(!empty(vaddrList),
@@ -418,7 +418,7 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
418418
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdataClass, isTFE>.ret;
419419

420420
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
421-
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
421+
dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
422422

423423
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
424424
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
@@ -703,7 +703,7 @@ class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in, bit hasRestric
703703
dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
704704
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
705705
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
706-
dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset));
706+
dag MainInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset));
707707
dag CPol = !if(vdata_in, (ins CPol_GLC_WithDefault:$cpol),
708708
(ins CPol_NonGLC_WithDefault:$cpol));
709709

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -279,7 +279,9 @@ DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
279279
DECODE_OPERAND_REG_7(SReg_64_XEXEC_XNULL, OPW64)
280280
DECODE_OPERAND_REG_7(SReg_96, OPW96)
281281
DECODE_OPERAND_REG_7(SReg_128, OPW128)
282+
DECODE_OPERAND_REG_7(SReg_128_XNULL, OPW128)
282283
DECODE_OPERAND_REG_7(SReg_256, OPW256)
284+
DECODE_OPERAND_REG_7(SReg_256_XNULL, OPW256)
283285
DECODE_OPERAND_REG_7(SReg_512, OPW512)
284286

285287
DECODE_OPERAND_REG_8(AGPR_32)
@@ -1692,6 +1694,11 @@ AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val,
16921694
case OPW64:
16931695
case OPWV232:
16941696
return decodeSpecialReg64(Val);
1697+
case OPW96:
1698+
case OPW128:
1699+
case OPW256:
1700+
case OPW512:
1701+
return decodeSpecialReg96Plus(Val);
16951702
default:
16961703
llvm_unreachable("unexpected immediate type");
16971704
}
@@ -1778,6 +1785,24 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
17781785
return errOperand(Val, "unknown operand encoding " + Twine(Val));
17791786
}
17801787

1788+
MCOperand AMDGPUDisassembler::decodeSpecialReg96Plus(unsigned Val) const {
1789+
using namespace AMDGPU;
1790+
1791+
switch (Val) {
1792+
case 124:
1793+
if (isGFX11Plus())
1794+
return createRegOperand(SGPR_NULL);
1795+
break;
1796+
case 125:
1797+
if (!isGFX11Plus())
1798+
return createRegOperand(SGPR_NULL);
1799+
break;
1800+
default:
1801+
break;
1802+
}
1803+
return errOperand(Val, "unknown operand encoding " + Twine(Val));
1804+
}
1805+
17811806
MCOperand
17821807
AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val,
17831808
unsigned ImmWidth,

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,7 @@ class AMDGPUDisassembler : public MCDisassembler {
259259
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
260260
MCOperand decodeSpecialReg32(unsigned Val) const;
261261
MCOperand decodeSpecialReg64(unsigned Val) const;
262+
MCOperand decodeSpecialReg96Plus(unsigned Val) const;
262263

263264
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
264265
unsigned ImmWidth,

‎llvm/lib/Target/AMDGPU/MIMGInstructions.td‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -422,7 +422,7 @@ class MIMG_NoSampler_Helper <mimgopc op, string asm,
422422
RegisterClass addr_rc,
423423
string dns="">
424424
: MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> {
425-
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
425+
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
426426
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
427427
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
428428
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -435,7 +435,7 @@ class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
435435
RegisterClass addr_rc,
436436
string dns="">
437437
: MIMG_gfx90a <op.GFX10M, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
438-
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
438+
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
439439
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
440440
R128A16:$r128, LWE:$lwe, DA:$da),
441441
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -447,7 +447,7 @@ class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
447447
RegisterClass DataRC, RegisterClass AddrRC,
448448
string dns="">
449449
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
450-
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
450+
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
451451
Dim:$dim, UNorm:$unorm, CPol:$cpol,
452452
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
453453
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -460,7 +460,7 @@ class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
460460
string dns="">
461461
: MIMG_nsa_gfx10<op.GFX10M, (outs DataRC:$vdata), num_addrs, dns> {
462462
let InOperandList = !con(AddrIns,
463-
(ins SReg_256:$srsrc, DMask:$dmask,
463+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
464464
Dim:$dim, UNorm:$unorm, CPol:$cpol,
465465
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
466466
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -472,7 +472,7 @@ class MIMG_NoSampler_gfx11<mimgopc op, string opcode,
472472
RegisterClass DataRC, RegisterClass AddrRC,
473473
string dns="">
474474
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
475-
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
475+
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
476476
Dim:$dim, UNorm:$unorm, CPol:$cpol,
477477
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
478478
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -485,7 +485,7 @@ class MIMG_NoSampler_nsa_gfx11<mimgopc op, string opcode,
485485
string dns="">
486486
: MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns> {
487487
let InOperandList = !con(AddrIns,
488-
(ins SReg_256:$srsrc, DMask:$dmask,
488+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
489489
Dim:$dim, UNorm:$unorm, CPol:$cpol,
490490
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
491491
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -498,7 +498,7 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
498498
string dns="">
499499
: VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
500500
let InOperandList = !con(AddrIns,
501-
(ins SReg_256:$rsrc, DMask:$dmask, Dim:$dim,
501+
(ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
502502
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
503503
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
504504
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -510,8 +510,8 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
510510
string dns="">
511511
: VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
512512
let InOperandList = !con(AddrIns,
513-
(ins SReg_256:$rsrc),
514-
!if(BaseOpcode.Sampler, (ins SReg_128:$samp), (ins)),
513+
(ins SReg_256_XNULL:$rsrc),
514+
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
515515
(ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
516516
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
517517
LWE:$lwe),
@@ -527,8 +527,8 @@ class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
527527
string dns="">
528528
: VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
529529
let InOperandList = !con(AddrIns,
530-
(ins SReg_256:$rsrc),
531-
!if(BaseOpcode.Sampler, (ins SReg_128:$samp), (ins)),
530+
(ins SReg_256_XNULL:$rsrc),
531+
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
532532
(ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
533533
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
534534
LWE:$lwe),
@@ -679,7 +679,7 @@ class MIMG_Store_Helper <mimgopc op, string asm,
679679
RegisterClass addr_rc,
680680
string dns = "">
681681
: MIMG_gfx6789<op.GFX10M, (outs), dns> {
682-
let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
682+
let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
683683
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
684684
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
685685
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -693,7 +693,7 @@ class MIMG_Store_Helper_gfx90a <mimgopc op, string asm,
693693
string dns = "">
694694
: MIMG_gfx90a<op.GFX10M, (outs), dns> {
695695
let InOperandList = !con((ins getLdStRegisterOperand<data_rc>.ret:$vdata,
696-
addr_rc:$vaddr, SReg_256:$srsrc,
696+
addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
697697
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
698698
R128A16:$r128, LWE:$lwe, DA:$da),
699699
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -705,7 +705,7 @@ class MIMG_Store_gfx10<mimgopc op, string opcode,
705705
RegisterClass DataRC, RegisterClass AddrRC,
706706
string dns="">
707707
: MIMG_gfx10<op.GFX10M, (outs), dns> {
708-
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
708+
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
709709
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
710710
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
711711
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -719,7 +719,7 @@ class MIMG_Store_nsa_gfx10<mimgopc op, string opcode,
719719
: MIMG_nsa_gfx10<op.GFX10M, (outs), num_addrs, dns> {
720720
let InOperandList = !con((ins DataRC:$vdata),
721721
AddrIns,
722-
(ins SReg_256:$srsrc, DMask:$dmask,
722+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
723723
Dim:$dim, UNorm:$unorm, CPol:$cpol,
724724
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
725725
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -731,7 +731,7 @@ class MIMG_Store_gfx11<mimgopc op, string opcode,
731731
RegisterClass DataRC, RegisterClass AddrRC,
732732
string dns="">
733733
: MIMG_gfx11<op.GFX11, (outs), dns> {
734-
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
734+
let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
735735
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
736736
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
737737
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -745,7 +745,7 @@ class MIMG_Store_nsa_gfx11<mimgopc op, string opcode,
745745
: MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns> {
746746
let InOperandList = !con((ins DataRC:$vdata),
747747
AddrIns,
748-
(ins SReg_256:$srsrc, DMask:$dmask,
748+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
749749
Dim:$dim, UNorm:$unorm, CPol:$cpol,
750750
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
751751
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -759,7 +759,7 @@ class VIMAGE_Store_gfx12<mimgopc op, string opcode,
759759
: VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
760760
let InOperandList = !con((ins DataRC:$vdata),
761761
AddrIns,
762-
(ins SReg_256:$rsrc, DMask:$dmask, Dim:$dim,
762+
(ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
763763
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
764764
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
765765
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -875,7 +875,7 @@ class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
875875
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
876876
let Constraints = "$vdst = $vdata";
877877

878-
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
878+
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
879879
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
880880
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
881881
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
@@ -887,7 +887,7 @@ class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
887887
let Constraints = "$vdst = $vdata";
888888

889889
let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata,
890-
addr_rc:$vaddr, SReg_256:$srsrc,
890+
addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
891891
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
892892
R128A16:$r128, LWE:$lwe, DA:$da);
893893
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$lwe$da";
@@ -921,7 +921,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
921921
!if(enableDisasm, "GFX10", "")> {
922922
let Constraints = "$vdst = $vdata";
923923

924-
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
924+
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
925925
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
926926
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
927927
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -936,7 +936,7 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
936936

937937
let InOperandList = !con((ins DataRC:$vdata),
938938
AddrIns,
939-
(ins SReg_256:$srsrc, DMask:$dmask,
939+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
940940
Dim:$dim, UNorm:$unorm, CPol:$cpol,
941941
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe));
942942
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -949,7 +949,7 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
949949
!if(enableDisasm, "GFX11", "")> {
950950
let Constraints = "$vdst = $vdata";
951951

952-
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
952+
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
953953
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
954954
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
955955
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -964,7 +964,7 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
964964

965965
let InOperandList = !con((ins DataRC:$vdata),
966966
AddrIns,
967-
(ins SReg_256:$srsrc, DMask:$dmask,
967+
(ins SReg_256_XNULL:$srsrc, DMask:$dmask,
968968
Dim:$dim, UNorm:$unorm, CPol:$cpol,
969969
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe));
970970
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -978,7 +978,7 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
978978

979979
let InOperandList = !con((ins DataRC:$vdata),
980980
AddrIns,
981-
(ins SReg_256:$rsrc, DMask:$dmask, Dim:$dim,
981+
(ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
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CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe));
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let AsmString = !if(!empty(renamed), opcode, renamed)#" $vdata, "#AddrAsm#
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", $rsrc$dmask$dim$cpol$r128$a16$tfe";
@@ -1128,7 +1128,7 @@ multiclass MIMG_Atomic_Renamed <mimgopc op, string asm, string renamed,
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class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
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RegisterClass src_rc, string dns="">
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: MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
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let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
1131+
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -1139,7 +1139,7 @@ class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
11391139
class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc,
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RegisterClass src_rc, string dns="">
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: MIMG_gfx90a<op.GFX10M, (outs getLdStRegisterOperand<dst_rc>.ret:$vdata), dns> {
1142-
let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
1142+
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
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DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -1149,7 +1149,7 @@ class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc,
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class MIMG_Sampler_OpList_gfx10p<dag OpPrefix, bit HasD16> {
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dag ret = !con(OpPrefix,
1152-
(ins SReg_256:$srsrc, SReg_128:$ssamp,
1152+
(ins SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
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DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
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R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
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!if(HasD16, (ins D16:$d16), (ins)));

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