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[AMDGPU][True16][MC] true16 for v_cos_f16 (llvm#120639)
Support true16 format for v_cos_f16 in MC
1 parent b71a6fd commit bf274b3

29 files changed

+1062
-462
lines changed

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1046,7 +1046,7 @@ defm V_TRUNC_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05d,
10461046
defm V_RNDNE_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05e, "v_rndne_f16">;
10471047
defm V_FRACT_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05f, "v_fract_f16">;
10481048
defm V_SIN_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x060, "v_sin_f16">;
1049-
defm V_COS_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x061, "v_cos_f16">;
1049+
defm V_COS_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x061, "v_cos_f16">;
10501050
defm V_SAT_PK_U8_I16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x062, "v_sat_pk_u8_i16">;
10511051
defm V_CVT_NORM_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x063, "v_cvt_norm_i16_f16">;
10521052
defm V_CVT_NORM_U16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x064, "v_cvt_norm_u16_f16">;

‎llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
55
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
66
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s
7+
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX12 %s
78

89
define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
910
; GFX6-LABEL: cos_f16:
@@ -80,6 +81,19 @@ define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
8081
; GFX11-NEXT: v_cos_f16_e32 v1, v1
8182
; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
8283
; GFX11-NEXT: s_endpgm
84+
;
85+
; GFX12-LABEL: cos_f16:
86+
; GFX12: ; %bb.0:
87+
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
88+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
89+
; GFX12-NEXT: s_wait_kmcnt 0x0
90+
; GFX12-NEXT: global_load_u16 v1, v0, s[2:3]
91+
; GFX12-NEXT: s_wait_loadcnt 0x0
92+
; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
93+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
94+
; GFX12-NEXT: v_cos_f16_e32 v1, v1
95+
; GFX12-NEXT: global_store_b16 v0, v1, s[0:1]
96+
; GFX12-NEXT: s_endpgm
8397
%a.val = load half, ptr addrspace(1) %a
8498
%r.val = call half @llvm.cos.f16(half %a.val)
8599
store half %r.val, ptr addrspace(1) %r
@@ -188,6 +202,24 @@ define amdgpu_kernel void @cos_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
188202
; GFX11-NEXT: v_pack_b32_f16 v1, v1, v2
189203
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
190204
; GFX11-NEXT: s_endpgm
205+
;
206+
; GFX12-LABEL: cos_v2f16:
207+
; GFX12: ; %bb.0:
208+
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
209+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
210+
; GFX12-NEXT: s_wait_kmcnt 0x0
211+
; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
212+
; GFX12-NEXT: s_wait_loadcnt 0x0
213+
; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v1
214+
; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
215+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
216+
; GFX12-NEXT: v_mul_f16_e32 v2, 0.15915494, v2
217+
; GFX12-NEXT: v_cos_f16_e32 v1, v1
218+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
219+
; GFX12-NEXT: v_cos_f16_e32 v2, v2
220+
; GFX12-NEXT: v_pack_b32_f16 v1, v1, v2
221+
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
222+
; GFX12-NEXT: s_endpgm
191223
%a.val = load <2 x half>, ptr addrspace(1) %a
192224
%r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val)
193225
store <2 x half> %r.val, ptr addrspace(1) %r

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1.s‎

Lines changed: 45 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -269,50 +269,65 @@ v_clz_i32_u32 v5, src_scc
269269
v_clz_i32_u32 v255, 0xaf123456
270270
// GFX11: v_clz_i32_u32_e32 v255, 0xaf123456 ; encoding: [0xff,0x72,0xfe,0x7f,0x56,0x34,0x12,0xaf]
271271

272-
v_cos_f16 v5, v1
273-
// GFX11: v_cos_f16_e32 v5, v1 ; encoding: [0x01,0xc3,0x0a,0x7e]
272+
v_cos_f16 v5.l, v1.l
273+
// GFX11: v_cos_f16_e32 v5.l, v1.l ; encoding: [0x01,0xc3,0x0a,0x7e]
274274

275-
v_cos_f16 v5, v127
276-
// GFX11: v_cos_f16_e32 v5, v127 ; encoding: [0x7f,0xc3,0x0a,0x7e]
275+
v_cos_f16 v5.l, v127.l
276+
// GFX11: v_cos_f16_e32 v5.l, v127.l ; encoding: [0x7f,0xc3,0x0a,0x7e]
277277

278-
v_cos_f16 v5, s1
279-
// GFX11: v_cos_f16_e32 v5, s1 ; encoding: [0x01,0xc2,0x0a,0x7e]
278+
v_cos_f16 v5.l, s1
279+
// GFX11: v_cos_f16_e32 v5.l, s1 ; encoding: [0x01,0xc2,0x0a,0x7e]
280280

281-
v_cos_f16 v5, s105
282-
// GFX11: v_cos_f16_e32 v5, s105 ; encoding: [0x69,0xc2,0x0a,0x7e]
281+
v_cos_f16 v5.l, s105
282+
// GFX11: v_cos_f16_e32 v5.l, s105 ; encoding: [0x69,0xc2,0x0a,0x7e]
283283

284-
v_cos_f16 v5, vcc_lo
285-
// GFX11: v_cos_f16_e32 v5, vcc_lo ; encoding: [0x6a,0xc2,0x0a,0x7e]
284+
v_cos_f16 v5.l, vcc_lo
285+
// GFX11: v_cos_f16_e32 v5.l, vcc_lo ; encoding: [0x6a,0xc2,0x0a,0x7e]
286286

287-
v_cos_f16 v5, vcc_hi
288-
// GFX11: v_cos_f16_e32 v5, vcc_hi ; encoding: [0x6b,0xc2,0x0a,0x7e]
287+
v_cos_f16 v5.l, vcc_hi
288+
// GFX11: v_cos_f16_e32 v5.l, vcc_hi ; encoding: [0x6b,0xc2,0x0a,0x7e]
289289

290-
v_cos_f16 v5, ttmp15
291-
// GFX11: v_cos_f16_e32 v5, ttmp15 ; encoding: [0x7b,0xc2,0x0a,0x7e]
290+
v_cos_f16 v5.l, ttmp15
291+
// GFX11: v_cos_f16_e32 v5.l, ttmp15 ; encoding: [0x7b,0xc2,0x0a,0x7e]
292292

293-
v_cos_f16 v5, m0
294-
// GFX11: v_cos_f16_e32 v5, m0 ; encoding: [0x7d,0xc2,0x0a,0x7e]
293+
v_cos_f16 v5.l, m0
294+
// GFX11: v_cos_f16_e32 v5.l, m0 ; encoding: [0x7d,0xc2,0x0a,0x7e]
295295

296-
v_cos_f16 v5, exec_lo
297-
// GFX11: v_cos_f16_e32 v5, exec_lo ; encoding: [0x7e,0xc2,0x0a,0x7e]
296+
v_cos_f16 v5.l, exec_lo
297+
// GFX11: v_cos_f16_e32 v5.l, exec_lo ; encoding: [0x7e,0xc2,0x0a,0x7e]
298298

299-
v_cos_f16 v5, exec_hi
300-
// GFX11: v_cos_f16_e32 v5, exec_hi ; encoding: [0x7f,0xc2,0x0a,0x7e]
299+
v_cos_f16 v5.l, exec_hi
300+
// GFX11: v_cos_f16_e32 v5.l, exec_hi ; encoding: [0x7f,0xc2,0x0a,0x7e]
301301

302-
v_cos_f16 v5, null
303-
// GFX11: v_cos_f16_e32 v5, null ; encoding: [0x7c,0xc2,0x0a,0x7e]
302+
v_cos_f16 v5.l, null
303+
// GFX11: v_cos_f16_e32 v5.l, null ; encoding: [0x7c,0xc2,0x0a,0x7e]
304304

305-
v_cos_f16 v5, -1
306-
// GFX11: v_cos_f16_e32 v5, -1 ; encoding: [0xc1,0xc2,0x0a,0x7e]
305+
v_cos_f16 v5.l, -1
306+
// GFX11: v_cos_f16_e32 v5.l, -1 ; encoding: [0xc1,0xc2,0x0a,0x7e]
307307

308-
v_cos_f16 v5, 0.5
309-
// GFX11: v_cos_f16_e32 v5, 0.5 ; encoding: [0xf0,0xc2,0x0a,0x7e]
308+
v_cos_f16 v5.l, 0.5
309+
// GFX11: v_cos_f16_e32 v5.l, 0.5 ; encoding: [0xf0,0xc2,0x0a,0x7e]
310310

311-
v_cos_f16 v5, src_scc
312-
// GFX11: v_cos_f16_e32 v5, src_scc ; encoding: [0xfd,0xc2,0x0a,0x7e]
311+
v_cos_f16 v5.l, src_scc
312+
// GFX11: v_cos_f16_e32 v5.l, src_scc ; encoding: [0xfd,0xc2,0x0a,0x7e]
313313

314-
v_cos_f16 v127, 0xfe0b
315-
// GFX11: v_cos_f16_e32 v127, 0xfe0b ; encoding: [0xff,0xc2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
314+
v_cos_f16 v127.l, 0xfe0b
315+
// GFX11: v_cos_f16_e32 v127.l, 0xfe0b ; encoding: [0xff,0xc2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
316+
317+
v_cos_f16 v5.l, v1.h
318+
// GFX11: v_cos_f16_e32 v5.l, v1.h ; encoding: [0x81,0xc3,0x0a,0x7e]
319+
320+
v_cos_f16 v5.l, v127.h
321+
// GFX11: v_cos_f16_e32 v5.l, v127.h ; encoding: [0xff,0xc3,0x0a,0x7e]
322+
323+
v_cos_f16 v127.l, 0.5
324+
// GFX11: v_cos_f16_e32 v127.l, 0.5 ; encoding: [0xf0,0xc2,0xfe,0x7e]
325+
326+
v_cos_f16 v5.h, src_scc
327+
// GFX11: v_cos_f16_e32 v5.h, src_scc ; encoding: [0xfd,0xc2,0x0a,0x7f]
328+
329+
v_cos_f16 v127.h, 0xfe0b
330+
// GFX11: v_cos_f16_e32 v127.h, 0xfe0b ; encoding: [0xff,0xc2,0xfe,0x7f,0x0b,0xfe,0x00,0x00]
316331

317332
v_cos_f32 v5, v1
318333
// GFX11: v_cos_f32_e32 v5, v1 ; encoding: [0x01,0x6d,0x0a,0x7e]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s‎

Lines changed: 37 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -212,47 +212,56 @@ v_clz_i32_u32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
212212
v_clz_i32_u32 v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
213213
// GFX11: v_clz_i32_u32_dpp v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x72,0xfe,0x7f,0xff,0x6f,0x05,0x30]
214214

215-
v_cos_f16 v5, v1 quad_perm:[3,2,1,0]
216-
// GFX11: v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
215+
v_cos_f16 v5.l, v1.l quad_perm:[3,2,1,0]
216+
// GFX11: v_cos_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
217217

218-
v_cos_f16 v5, v1 quad_perm:[0,1,2,3]
219-
// GFX11: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
218+
v_cos_f16 v5.l, v1.l quad_perm:[0,1,2,3]
219+
// GFX11: v_cos_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
220220

221-
v_cos_f16 v5, v1 row_mirror
222-
// GFX11: v_cos_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0xff]
221+
v_cos_f16 v5.l, v1.l row_mirror
222+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0xff]
223223

224-
v_cos_f16 v5, v1 row_half_mirror
225-
// GFX11: v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0xff]
224+
v_cos_f16 v5.l, v1.l row_half_mirror
225+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0xff]
226226

227-
v_cos_f16 v5, v1 row_shl:1
228-
// GFX11: v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0xff]
227+
v_cos_f16 v5.l, v1.l row_shl:1
228+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0xff]
229229

230-
v_cos_f16 v5, v1 row_shl:15
231-
// GFX11: v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
230+
v_cos_f16 v5.l, v1.l row_shl:15
231+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
232232

233-
v_cos_f16 v5, v1 row_shr:1
234-
// GFX11: v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0xff]
233+
v_cos_f16 v5.l, v1.l row_shr:1
234+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0xff]
235235

236-
v_cos_f16 v5, v1 row_shr:15
237-
// GFX11: v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
236+
v_cos_f16 v5.l, v1.l row_shr:15
237+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
238238

239-
v_cos_f16 v5, v1 row_ror:1
240-
// GFX11: v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0xff]
239+
v_cos_f16 v5.l, v1.l row_ror:1
240+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0xff]
241241

242-
v_cos_f16 v5, v1 row_ror:15
243-
// GFX11: v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
242+
v_cos_f16 v5.l, v1.l row_ror:15
243+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
244244

245-
v_cos_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
246-
// GFX11: v_cos_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x50,0x01,0xff]
245+
v_cos_f16 v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf
246+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x50,0x01,0xff]
247247

248-
v_cos_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
249-
// GFX11: v_cos_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
248+
v_cos_f16 v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1
249+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
250250

251-
v_cos_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
252-
// GFX11: v_cos_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x60,0x09,0x13]
251+
v_cos_f16 v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
252+
// GFX11: v_cos_f16_dpp v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x60,0x09,0x13]
253253

254-
v_cos_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
255-
// GFX11: v_cos_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
254+
v_cos_f16 v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
255+
// GFX11: v_cos_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
256+
257+
v_cos_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
258+
// GFX11: v_cos_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]
259+
260+
v_cos_f16 v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
261+
// GFX11: v_cos_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xc2,0x0a,0x7f,0x81,0x60,0x09,0x13]
262+
263+
v_cos_f16 v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
264+
// GFX11: v_cos_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xc2,0xfe,0x7f,0xff,0x6f,0x35,0x30]
256265

257266
v_cos_f32 v5, v1 quad_perm:[3,2,1,0]
258267
// GFX11: v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0xff]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s‎

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,14 +50,23 @@ v_clz_i32_u32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
5050
v_clz_i32_u32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
5151
// GFX11: v_clz_i32_u32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x72,0xfe,0x7f,0xff,0x00,0x00,0x00]
5252

53-
v_cos_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
54-
// GFX11: v_cos_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
53+
v_cos_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
54+
// GFX11: v_cos_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
5555

56-
v_cos_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
57-
// GFX11: v_cos_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
56+
v_cos_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1
57+
// GFX11: v_cos_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc2,0x0a,0x7e,0x01,0x77,0x39,0x05]
5858

59-
v_cos_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
60-
// GFX11: v_cos_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
59+
v_cos_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
60+
// GFX11: v_cos_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
61+
62+
v_cos_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
63+
// GFX11: v_cos_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xc2,0xfe,0x7e,0x7f,0x77,0x39,0x05]
64+
65+
v_cos_f16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
66+
// GFX11: v_cos_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xc2,0x0a,0x7f,0x81,0x77,0x39,0x05]
67+
68+
v_cos_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
69+
// GFX11: v_cos_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xc2,0xfe,0x7f,0xff,0x00,0x00,0x00]
6170

6271
v_cos_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
6372
// GFX11: v_cos_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x6c,0x0a,0x7e,0x01,0x77,0x39,0x05]

‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,12 @@ v_ceil_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
4747
v_cos_f16_e32 v128, 0xfe0b
4848
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
4949

50+
v_cos_f16_e32 v128.h, 0xfe0b
51+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
52+
53+
v_cos_f16_e32 v128.l, 0xfe0b
54+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
55+
5056
v_cos_f16_e32 v255, v1
5157
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
5258

@@ -56,6 +62,24 @@ v_cos_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
5662
v_cos_f16_e32 v255, v1 quad_perm:[3,2,1,0]
5763
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
5864

65+
v_cos_f16_e32 v255.h, v1.h
66+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
67+
68+
v_cos_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
69+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
70+
71+
v_cos_f16_e32 v255.h, v1.h quad_perm:[3,2,1,0]
72+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
73+
74+
v_cos_f16_e32 v255.l, v1.l
75+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
76+
77+
v_cos_f16_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
78+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
79+
80+
v_cos_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
81+
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction
82+
5983
v_cos_f16_e32 v5, v199
6084
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
6185

@@ -65,6 +89,24 @@ v_cos_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
6589
v_cos_f16_e32 v5, v199 quad_perm:[3,2,1,0]
6690
// GFX11: :[[@LINE-1]]:24: error: invalid operand for instruction
6791

92+
v_cos_f16_e32 v5.h, v199.h
93+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
94+
95+
v_cos_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
96+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
97+
98+
v_cos_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
99+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
100+
101+
v_cos_f16_e32 v5.l, v199.l
102+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
103+
104+
v_cos_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
105+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
106+
107+
v_cos_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
108+
// GFX11: :[[@LINE-1]]:21: error: invalid operand for instruction
109+
68110
v_cvt_f16_f32_e32 v128, 0xaf123456
69111
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
70112

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