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[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (llvm#115101)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to remove i32 from the GPR register class. I've added 2 custom nodes for CTZW and CLZW to match SelectionDAG. For cpopw we pattern match G_AND+G_CTPOP in isel.
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10 files changed

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-107
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
225225
auto &CountZerosUndefActions =
226226
getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF});
227227
if (ST.hasStdExtZbb()) {
228-
CountZerosActions.legalFor({{s32, s32}, {sXLen, sXLen}})
228+
CountZerosActions.legalFor({{sXLen, sXLen}})
229+
.customFor({{s32, s32}})
229230
.clampScalar(0, s32, sXLen)
230231
.widenScalarToNextPow2(0)
231232
.scalarSameSizeAs(1, 0);
@@ -237,9 +238,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
237238

238239
auto &CTPOPActions = getActionDefinitionsBuilder(G_CTPOP);
239240
if (ST.hasStdExtZbb()) {
240-
CTPOPActions.legalFor({{s32, s32}, {sXLen, sXLen}})
241-
.clampScalar(0, s32, sXLen)
242-
.widenScalarToNextPow2(0)
241+
CTPOPActions.legalFor({{sXLen, sXLen}})
242+
.clampScalar(0, sXLen, sXLen)
243243
.scalarSameSizeAs(1, 0);
244244
} else {
245245
CTPOPActions.maxScalar(0, sXLen).scalarSameSizeAs(1, 0).lower();
@@ -1158,6 +1158,17 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
11581158
return true;
11591159
}
11601160

1161+
static unsigned getRISCVWOpcode(unsigned Opcode) {
1162+
switch (Opcode) {
1163+
default:
1164+
llvm_unreachable("Unexpected opcode");
1165+
case TargetOpcode::G_CTLZ:
1166+
return RISCV::G_CLZW;
1167+
case TargetOpcode::G_CTTZ:
1168+
return RISCV::G_CTZW;
1169+
}
1170+
}
1171+
11611172
bool RISCVLegalizerInfo::legalizeCustom(
11621173
LegalizerHelper &Helper, MachineInstr &MI,
11631174
LostDebugLocObserver &LocObserver) const {
@@ -1194,6 +1205,15 @@ bool RISCVLegalizerInfo::legalizeCustom(
11941205
return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
11951206
LegalizerHelper::Legalized;
11961207
}
1208+
case TargetOpcode::G_CTLZ:
1209+
case TargetOpcode::G_CTTZ: {
1210+
Helper.Observer.changingInstr(MI);
1211+
Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT);
1212+
Helper.widenScalarDst(MI, sXLen);
1213+
MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode())));
1214+
Helper.Observer.changedInstr(MI);
1215+
return true;
1216+
}
11971217
case TargetOpcode::G_IS_FPCLASS: {
11981218
Register GISFPCLASS = MI.getOperand(0).getReg();
11991219
Register Src = MI.getOperand(1).getReg();

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -264,10 +264,6 @@ def : PatGprGpr<urem, REMUW, i32, i32>;
264264
//===----------------------------------------------------------------------===//
265265

266266
let Predicates = [HasStdExtZbb, IsRV64] in {
267-
def : PatGpr<ctlz, CLZW, i32>;
268-
def : PatGpr<cttz, CTZW, i32>;
269-
def : PatGpr<ctpop, CPOPW, i32>;
270-
271267
def : Pat<(i32 (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
272268
def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
273269

‎llvm/lib/Target/RISCV/RISCVInstrGISel.td‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,22 @@ class RISCVGenericInstruction : GenericInstruction {
1717
let Namespace = "RISCV";
1818
}
1919

20+
// Pseudo equivalent to a RISCVISD::CLZW.
21+
def G_CLZW : RISCVGenericInstruction {
22+
let OutOperandList = (outs type0:$dst);
23+
let InOperandList = (ins type0:$src);
24+
let hasSideEffects = false;
25+
}
26+
def : GINodeEquiv<G_CLZW, riscv_clzw>;
27+
28+
// Pseudo equivalent to a RISCVISD::CTZW.
29+
def G_CTZW : RISCVGenericInstruction {
30+
let OutOperandList = (outs type0:$dst);
31+
let InOperandList = (ins type0:$src);
32+
let hasSideEffects = false;
33+
}
34+
def : GINodeEquiv<G_CTZW, riscv_ctzw>;
35+
2036
// Pseudo equivalent to a RISCVISD::FCLASS.
2137
def G_FCLASS : RISCVGenericInstruction {
2238
let OutOperandList = (outs type0:$dst);

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctlz-rv64.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,8 @@ body: |
1515
; RV64I-NEXT: $x10 = COPY [[CLZW]]
1616
; RV64I-NEXT: PseudoRET implicit $x10
1717
%0:gprb(s64) = COPY $x10
18-
%1:gprb(s32) = G_TRUNC %0
19-
%2:gprb(s32) = G_CTLZ %1
20-
%3:gprb(s64) = G_ANYEXT %2
21-
$x10 = COPY %3(s64)
18+
%1:gprb(s64) = G_CLZW %0
19+
$x10 = COPY %1(s64)
2220
PseudoRET implicit $x10
2321
2422
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ctpop-rv64.mir‎

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -3,25 +3,6 @@
33
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
44
# RUN: | FileCheck -check-prefix=RV64I %s
55

6-
---
7-
name: ctpop_s32
8-
legalized: true
9-
regBankSelected: true
10-
body: |
11-
bb.0.entry:
12-
; RV64I-LABEL: name: ctpop_s32
13-
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14-
; RV64I-NEXT: [[CPOPW:%[0-9]+]]:gpr = CPOPW [[COPY]]
15-
; RV64I-NEXT: $x10 = COPY [[CPOPW]]
16-
; RV64I-NEXT: PseudoRET implicit $x10
17-
%0:gprb(s64) = COPY $x10
18-
%1:gprb(s32) = G_TRUNC %0
19-
%2:gprb(s32) = G_CTPOP %1
20-
%3:gprb(s64) = G_ANYEXT %2
21-
$x10 = COPY %3(s64)
22-
PseudoRET implicit $x10
23-
24-
...
256
---
267
name: ctpop_s64
278
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cttz-rv64.mir‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,8 @@ body: |
1515
; RV64I-NEXT: $x10 = COPY [[CTZW]]
1616
; RV64I-NEXT: PseudoRET implicit $x10
1717
%0:gprb(s64) = COPY $x10
18-
%1:gprb(s32) = G_TRUNC %0
19-
%2:gprb(s32) = G_CTTZ %1
20-
%3:gprb(s64) = G_ANYEXT %2
21-
$x10 = COPY %3(s64)
18+
%1:gprb(s64) = G_CTZW %0
19+
$x10 = COPY %1(s64)
2220
PseudoRET implicit $x10
2321
2422
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir‎

Lines changed: 24 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -57,12 +57,12 @@ body: |
5757
; RV64ZBB: liveins: $x10
5858
; RV64ZBB-NEXT: {{ $}}
5959
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
60-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
61-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
62-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
63-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
60+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
61+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
62+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
63+
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
6464
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
65-
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
65+
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
6666
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
6767
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
6868
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -133,12 +133,12 @@ body: |
133133
; RV64ZBB: liveins: $x10
134134
; RV64ZBB-NEXT: {{ $}}
135135
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
136-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
137-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
138-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
139-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
136+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
137+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
138+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
139+
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
140140
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
141-
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
141+
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
142142
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
143143
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
144144
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -204,10 +204,8 @@ body: |
204204
; RV64ZBB: liveins: $x10
205205
; RV64ZBB-NEXT: {{ $}}
206206
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
207-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
208-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[TRUNC]](s32)
209-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTLZ]](s32)
210-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
207+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]]
208+
; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64)
211209
; RV64ZBB-NEXT: PseudoRET implicit $x10
212210
%1:_(s64) = COPY $x10
213211
%0:_(s32) = G_TRUNC %1(s64)
@@ -333,12 +331,12 @@ body: |
333331
; RV64ZBB: liveins: $x10
334332
; RV64ZBB-NEXT: {{ $}}
335333
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
336-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
337-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
338-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
339-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
334+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
335+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
336+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
337+
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
340338
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
341-
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
339+
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
342340
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
343341
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
344342
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -409,12 +407,12 @@ body: |
409407
; RV64ZBB: liveins: $x10
410408
; RV64ZBB-NEXT: {{ $}}
411409
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
412-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
413-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
414-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
415-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
410+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
411+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
412+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]]
413+
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[CLZW]](s64)
416414
; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
417-
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]]
415+
; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[C1]]
418416
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
419417
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
420418
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
@@ -480,10 +478,8 @@ body: |
480478
; RV64ZBB: liveins: $x10
481479
; RV64ZBB-NEXT: {{ $}}
482480
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
483-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
484-
; RV64ZBB-NEXT: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[TRUNC]](s32)
485-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTLZ]](s32)
486-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
481+
; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[COPY]]
482+
; RV64ZBB-NEXT: $x10 = COPY [[CLZW]](s64)
487483
; RV64ZBB-NEXT: PseudoRET implicit $x10
488484
%1:_(s64) = COPY $x10
489485
%0:_(s32) = G_TRUNC %1(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir‎

Lines changed: 15 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -46,13 +46,11 @@ body: |
4646
; RV64ZBB: liveins: $x10
4747
; RV64ZBB-NEXT: {{ $}}
4848
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
49-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
50-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
51-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
52-
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
53-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
54-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
55-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
49+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
50+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
51+
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
52+
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
53+
; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
5654
; RV64ZBB-NEXT: PseudoRET implicit $x10
5755
%1:_(s64) = COPY $x10
5856
%0:_(s8) = G_TRUNC %1(s64)
@@ -106,13 +104,11 @@ body: |
106104
; RV64ZBB: liveins: $x10
107105
; RV64ZBB-NEXT: {{ $}}
108106
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
109-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
110-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
111-
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
112-
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
113-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
114-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
115-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
107+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
108+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
109+
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
110+
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
111+
; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
116112
; RV64ZBB-NEXT: PseudoRET implicit $x10
117113
%1:_(s64) = COPY $x10
118114
%0:_(s16) = G_TRUNC %1(s64)
@@ -161,10 +157,11 @@ body: |
161157
; RV64ZBB: liveins: $x10
162158
; RV64ZBB-NEXT: {{ $}}
163159
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
164-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
165-
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[TRUNC]](s32)
166-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTPOP]](s32)
167-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
160+
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
161+
; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
162+
; RV64ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s64) = G_CTPOP [[AND]](s64)
163+
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[CTPOP]](s64)
164+
; RV64ZBB-NEXT: $x10 = COPY [[COPY1]](s64)
168165
; RV64ZBB-NEXT: PseudoRET implicit $x10
169166
%1:_(s64) = COPY $x10
170167
%0:_(s32) = G_TRUNC %1(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir‎

Lines changed: 16 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -52,10 +52,9 @@ body: |
5252
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
5353
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
5454
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
55-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
56-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
57-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
58-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
55+
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
56+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
57+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
5958
; RV64ZBB-NEXT: PseudoRET implicit $x10
6059
%1:_(s64) = COPY $x10
6160
%0:_(s8) = G_TRUNC %1(s64)
@@ -115,10 +114,9 @@ body: |
115114
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
116115
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
117116
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
118-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
119-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
120-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
121-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
117+
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
118+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
119+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
122120
; RV64ZBB-NEXT: PseudoRET implicit $x10
123121
%1:_(s64) = COPY $x10
124122
%0:_(s16) = G_TRUNC %1(s64)
@@ -171,10 +169,8 @@ body: |
171169
; RV64ZBB: liveins: $x10
172170
; RV64ZBB-NEXT: {{ $}}
173171
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
174-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
175-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[TRUNC]](s32)
176-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTTZ]](s32)
177-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
172+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]]
173+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
178174
; RV64ZBB-NEXT: PseudoRET implicit $x10
179175
%1:_(s64) = COPY $x10
180176
%0:_(s32) = G_TRUNC %1(s64)
@@ -282,10 +278,9 @@ body: |
282278
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
283279
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
284280
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
285-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
286-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
287-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
288-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
281+
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
282+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
283+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
289284
; RV64ZBB-NEXT: PseudoRET implicit $x10
290285
%1:_(s64) = COPY $x10
291286
%0:_(s8) = G_TRUNC %1(s64)
@@ -345,10 +340,9 @@ body: |
345340
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
346341
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
347342
; RV64ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[C]]
348-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)
349-
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)
350-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
351-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
343+
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
344+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[ANYEXT]]
345+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
352346
; RV64ZBB-NEXT: PseudoRET implicit $x10
353347
%1:_(s64) = COPY $x10
354348
%0:_(s16) = G_TRUNC %1(s64)
@@ -401,10 +395,8 @@ body: |
401395
; RV64ZBB: liveins: $x10
402396
; RV64ZBB-NEXT: {{ $}}
403397
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
404-
; RV64ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
405-
; RV64ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[TRUNC]](s32)
406-
; RV64ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CTTZ]](s32)
407-
; RV64ZBB-NEXT: $x10 = COPY [[ANYEXT]](s64)
398+
; RV64ZBB-NEXT: [[CTZW:%[0-9]+]]:_(s64) = G_CTZW [[COPY]]
399+
; RV64ZBB-NEXT: $x10 = COPY [[CTZW]](s64)
408400
; RV64ZBB-NEXT: PseudoRET implicit $x10
409401
%1:_(s64) = COPY $x10
410402
%0:_(s32) = G_TRUNC %1(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -752,8 +752,6 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {
752752
; RV64ZBB-LABEL: ctpop_i32_ult_two:
753753
; RV64ZBB: # %bb.0:
754754
; RV64ZBB-NEXT: cpopw a0, a0
755-
; RV64ZBB-NEXT: slli a0, a0, 32
756-
; RV64ZBB-NEXT: srli a0, a0, 32
757755
; RV64ZBB-NEXT: sltiu a0, a0, 2
758756
; RV64ZBB-NEXT: ret
759757
%1 = call i32 @llvm.ctpop.i32(i32 %a)
@@ -794,6 +792,8 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind {
794792
; RV64ZBB-LABEL: ctpop_i32_load:
795793
; RV64ZBB: # %bb.0:
796794
; RV64ZBB-NEXT: lw a0, 0(a0)
795+
; RV64ZBB-NEXT: slli a0, a0, 32
796+
; RV64ZBB-NEXT: srli a0, a0, 32
797797
; RV64ZBB-NEXT: cpopw a0, a0
798798
; RV64ZBB-NEXT: ret
799799
%a = load i32, ptr %p

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