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RKSimonRKSimon
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[X86] combineINSERT_SUBVECTOR - generalise insert_subvector(x,extract(broadcast)) -> blend (llvm#140516)
Don't match against specific broadcast nodes and let isShuffleEquivalent handle it
1 parent d827588 commit dec214d

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6 files changed

+26
-29
lines changed

6 files changed

+26
-29
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 20 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -59284,36 +59284,34 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
5928459284
!(Vec.isUndef() || ISD::isBuildVectorAllZeros(Vec.getNode())))) {
5928559285
SDValue ExtSrc = SubVec.getOperand(0);
5928659286
int ExtIdxVal = SubVec.getConstantOperandVal(1);
59287-
if (ExtIdxVal != 0) {
59288-
SmallVector<int, 64> Mask(VecNumElts);
59289-
// First create an identity shuffle mask.
59290-
for (int i = 0; i != VecNumElts; ++i)
59291-
Mask[i] = i;
59292-
// Now insert the extracted portion.
59293-
for (int i = 0; i != SubVecNumElts; ++i)
59294-
Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts;
59287+
// Create a shuffle mask matching the extraction and insertion.
59288+
SmallVector<int, 64> Mask(VecNumElts);
59289+
std::iota(Mask.begin(), Mask.end(), 0);
59290+
std::iota(Mask.begin() + IdxVal, Mask.begin() + IdxVal + SubVecNumElts,
59291+
ExtIdxVal + VecNumElts);
59292+
if (ExtIdxVal != 0)
5929559293
return DAG.getVectorShuffle(OpVT, dl, Vec, ExtSrc, Mask);
59296-
}
59297-
// If we're broadcasting, see if we can use a blend instead of
59298-
// extract/insert pair. Ensure that the subvector is aligned with the
59299-
// insertion/extractions.
59300-
if ((ExtIdxVal % SubVecNumElts) == 0 && (IdxVal % SubVecNumElts) == 0 &&
59301-
(ExtSrc.getOpcode() == X86ISD::VBROADCAST ||
59302-
ExtSrc.getOpcode() == X86ISD::VBROADCAST_LOAD ||
59303-
(ExtSrc.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD &&
59304-
cast<MemIntrinsicSDNode>(ExtSrc)->getMemoryVT() == SubVecVT))) {
59294+
// See if we can use a blend instead of extract/insert pair.
59295+
SmallVector<int, 64> BlendMask(VecNumElts);
59296+
std::iota(BlendMask.begin(), BlendMask.end(), 0);
59297+
std::iota(BlendMask.begin() + IdxVal,
59298+
BlendMask.begin() + IdxVal + SubVecNumElts, VecNumElts + IdxVal);
59299+
if (isShuffleEquivalent(Mask, BlendMask, Vec, ExtSrc) &&
59300+
VecNumElts == (2 * SubVecNumElts)) {
59301+
assert((IdxVal == 0 || IdxVal == SubVecNumElts) &&
59302+
"Unaligned subvector insertion");
5930559303
if (OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
59306-
uint64_t BlendMask = IdxVal == 0 ? 0x0F : 0xF0;
5930759304
SDValue Blend = DAG.getNode(
5930859305
X86ISD::BLENDI, dl, MVT::v8f32, DAG.getBitcast(MVT::v8f32, Vec),
5930959306
DAG.getBitcast(MVT::v8f32, ExtSrc),
59310-
DAG.getTargetConstant(BlendMask, dl, MVT::i8));
59307+
DAG.getTargetConstant(IdxVal == 0 ? 0x0F : 0xF0, dl, MVT::i8));
5931159308
return DAG.getBitcast(OpVT, Blend);
5931259309
} else if (OpVT.is512BitVector() && SubVecVT.is256BitVector()) {
59313-
SDValue Lo = DAG.getBitcast(MVT::v8f64, IdxVal == 0 ? ExtSrc : Vec);
59314-
SDValue Hi = DAG.getBitcast(MVT::v8f64, IdxVal == 0 ? Vec : ExtSrc);
59310+
MVT ShufVT = OpVT.isInteger() ? MVT::v8i64 : MVT::v8f64;
59311+
SDValue Lo = DAG.getBitcast(ShufVT, IdxVal == 0 ? ExtSrc : Vec);
59312+
SDValue Hi = DAG.getBitcast(ShufVT, IdxVal == 0 ? Vec : ExtSrc);
5931559313
SDValue Shuffle =
59316-
DAG.getNode(X86ISD::SHUF128, dl, MVT::v8f64, Lo, Hi,
59314+
DAG.getNode(X86ISD::SHUF128, dl, ShufVT, Lo, Hi,
5931759315
getV4X86ShuffleImm8ForMask({0, 1, 2, 3}, dl, DAG));
5931859316
return DAG.getBitcast(OpVT, Shuffle);
5931959317
}

‎llvm/test/CodeGen/X86/insert-subvector-broadcast.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,8 @@ define void @insert_subvector_broadcast_as_blend() {
77
; CHECK-NEXT: movq (%rax), %rax
88
; CHECK-NEXT: incq %rax
99
; CHECK-NEXT: vpbroadcastq %rax, %zmm0
10-
; CHECK-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
11-
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
12-
; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 = zmm1[0,1,2,3],zmm0[4,5,6,7]
10+
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
11+
; CHECK-NEXT: valignq {{.*#+}} zmm1 = zmm1[7],zmm0[0,1,2,3,4,5,6]
1312
; CHECK-NEXT: vpcmpltq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %k0
1413
; CHECK-NEXT: vpcmpltq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %k1
1514
; CHECK-NEXT: kunpckbw %k0, %k1, %k1

‎llvm/test/CodeGen/X86/widen_fadd.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ define void @widen_fadd_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
221221
; AVX512F-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
222222
; AVX512F-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
223223
; AVX512F-NEXT: vpermt2pd %zmm2, %zmm5, %zmm0
224-
; AVX512F-NEXT: vinsertf64x4 $0, %ymm0, %zmm4, %zmm0
224+
; AVX512F-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm4[4,5,6,7]
225225
; AVX512F-NEXT: vmovupd %zmm0, (%rdx)
226226
; AVX512F-NEXT: vzeroupper
227227
; AVX512F-NEXT: retq

‎llvm/test/CodeGen/X86/widen_fdiv.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ define void @widen_fdiv_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
182182
; AVX512F-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
183183
; AVX512F-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
184184
; AVX512F-NEXT: vpermt2pd %zmm2, %zmm5, %zmm0
185-
; AVX512F-NEXT: vinsertf64x4 $0, %ymm0, %zmm4, %zmm0
185+
; AVX512F-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm4[4,5,6,7]
186186
; AVX512F-NEXT: vmovupd %zmm0, (%rdx)
187187
; AVX512F-NEXT: vzeroupper
188188
; AVX512F-NEXT: retq

‎llvm/test/CodeGen/X86/widen_fmul.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ define void @widen_fmul_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
221221
; AVX512F-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
222222
; AVX512F-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
223223
; AVX512F-NEXT: vpermt2pd %zmm2, %zmm5, %zmm0
224-
; AVX512F-NEXT: vinsertf64x4 $0, %ymm0, %zmm4, %zmm0
224+
; AVX512F-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm4[4,5,6,7]
225225
; AVX512F-NEXT: vmovupd %zmm0, (%rdx)
226226
; AVX512F-NEXT: vzeroupper
227227
; AVX512F-NEXT: retq

‎llvm/test/CodeGen/X86/widen_fsub.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ define void @widen_fsub_v2f32_v16f32(ptr %a0, ptr %b0, ptr %c0) {
221221
; AVX512F-NEXT: vinsertf32x4 $1, %xmm3, %zmm2, %zmm2
222222
; AVX512F-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm0
223223
; AVX512F-NEXT: vpermt2pd %zmm2, %zmm5, %zmm0
224-
; AVX512F-NEXT: vinsertf64x4 $0, %ymm0, %zmm4, %zmm0
224+
; AVX512F-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm4[4,5,6,7]
225225
; AVX512F-NEXT: vmovupd %zmm0, (%rdx)
226226
; AVX512F-NEXT: vzeroupper
227227
; AVX512F-NEXT: retq

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