Measure the frequency hopping time and PLL locking time of the Libre VNA using ChipScope in ISE 14.7

[abczzz123]

I want to measure the frequency hopping time of the Libre VNA using ChipScope in ISE 14.7. The signals I observe are the rising edge of reload_plls and the rising edge of sampling_start. The frequency hopping time is calculated as the difference in the number of sampling points between these two edges multiplied by the clk_pll period. The sampling depth is set to 8K, and the position is set to 100. However, no matter how I adjust the IFBW (Intermediate Frequency Bandwidth) and PLL settling delay in the upper computer, the captured waveform always shows that the rising edge of reload_plls is at point -0.5, and the rising edge of sampling_start is at point 3370.5. How should I obtain the correct waveform, or how can I properly measure the frequency hopping time and PLL locking time?

[jankae]

I am not familiar with ChipScope, so I can not quite follow your numbers here (not sure what position at 100 means and how you can have points with decimals). But in general, your approach sounds like it should work.

I would probably probe the actual hardware signals:

• SPI SCK pin to the PLLs
• lock indicator from the PLLs
• ADC CNVST signal

For each frequency step in the sweep, you will see the following:

1. A burst on the SCK to the PLLs as they are configured for the new frequency
2. Shortly after the lock indicator will go high, indicating that the PLLs are locked
3. A number of pulses on CNVST (the actual ADC samples)

Changing the PLL settling delay will change the time delay between 2 and 3. Changing the IF bandwidth will change the number of ADC samples (pulses in 3).

[abczzz123]

Thank you for your valuable suggestions,I will carefully adopt them.