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[TableGen] Replace WantRoot/WantParent SDNode properties with flags (llvm#119599)
These properties are only valid on ComplexPatterns. Having them as flags is more convenient because one can now use "let = ... in" syntax to set these flags on several patterns at a time. This is also less error-prone as it makes it impossible to specify these properties on records derived from SDPatternOperator. Pull Request: llvm#119599
1 parent 4993a30 commit 6b22326

19 files changed

+95
-82
lines changed

‎llvm/include/llvm/CodeGen/SDNodeProperties.td‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,5 +29,3 @@ def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
2929
def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
3030
def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
3131
def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
32-
def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
33-
def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent

‎llvm/include/llvm/Target/TargetSelectionDAG.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2086,4 +2086,12 @@ class ComplexPattern<ValueType ty, int numops, string fn,
20862086
list<SDNode> RootNodes = roots;
20872087
list<SDNodeProperty> Properties = props;
20882088
int Complexity = complexity;
2089+
2090+
// Set this to true if SelectFunc wants an additional argument
2091+
// that is the root of the matched pattern.
2092+
bit WantsRoot = false;
2093+
2094+
// Set this to true if SelectFunc wants an additional argument
2095+
// that is the parent of the matched node.
2096+
bit WantsParent = false;
20892097
}

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ def tileslicerange2s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<12, 4>", []>;
3232
def tileslicerange1s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<4, 4>", []>;
3333
def tileslicerange0s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<0, 4>", []>;
3434

35-
def am_sme_indexed_b4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0,15>", [], [SDNPWantRoot]>;
35+
let WantsRoot = true in
36+
def am_sme_indexed_b4 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0, 15>">;
3637

3738
def SDTZALoadStore : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>]>;
3839
def AArch64SMELdr : SDNode<"AArch64ISD::SME_ZA_LDR", SDTZALoadStore,

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9567,8 +9567,10 @@ multiclass sve_int_perm_bin_perm_128_zz<bits<2> opc, bit P, string asm, SDPatter
95679567
}
95689568

95699569
/// Addressing modes
9570-
def am_sve_indexed_s4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-8,7>", [], [SDNPWantRoot]>;
9571-
def am_sve_indexed_s6 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-32,31>", [], [SDNPWantRoot]>;
9570+
let WantsRoot = true in {
9571+
def am_sve_indexed_s4 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-8, 7>">;
9572+
def am_sve_indexed_s6 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-32, 31>">;
9573+
}
95729574

95739575
def am_sve_regreg_lsl0 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<0>", []>;
95749576
def am_sve_regreg_lsl1 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<1>", []>;

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,10 @@
99
def MUBUFAddr64 : ComplexPattern<iPTR, 4, "SelectMUBUFAddr64">;
1010
def MUBUFOffset : ComplexPattern<iPTR, 3, "SelectMUBUFOffset">;
1111

12-
def MUBUFScratchOffen : ComplexPattern<iPTR, 4, "SelectMUBUFScratchOffen", [], [SDNPWantParent]>;
13-
def MUBUFScratchOffset : ComplexPattern<iPTR, 3, "SelectMUBUFScratchOffset", [], [SDNPWantParent], 20>;
12+
let WantsParent = true in {
13+
def MUBUFScratchOffen : ComplexPattern<iPTR, 4, "SelectMUBUFScratchOffen">;
14+
def MUBUFScratchOffset : ComplexPattern<iPTR, 3, "SelectMUBUFScratchOffset", [], [], 20>;
15+
}
1416

1517
def BUFSOffset : ComplexPattern<iPTR, 1, "SelectBUFSOffset">;
1618

‎llvm/lib/Target/AMDGPU/FLATInstructions.td‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,15 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
def FlatOffset : ComplexPattern<iPTR, 2, "SelectFlatOffset", [], [SDNPWantRoot], -10>;
10-
def GlobalOffset : ComplexPattern<iPTR, 2, "SelectGlobalOffset", [], [SDNPWantRoot], -10>;
11-
def ScratchOffset : ComplexPattern<iPTR, 2, "SelectScratchOffset", [], [SDNPWantRoot], -10>;
9+
let WantsRoot = true in {
10+
def FlatOffset : ComplexPattern<iPTR, 2, "SelectFlatOffset", [], [], -10>;
11+
def GlobalOffset : ComplexPattern<iPTR, 2, "SelectGlobalOffset", [], [], -10>;
12+
def ScratchOffset : ComplexPattern<iPTR, 2, "SelectScratchOffset", [], [], -10>;
1213

13-
def GlobalSAddr : ComplexPattern<iPTR, 3, "SelectGlobalSAddr", [], [SDNPWantRoot], -10>;
14-
def ScratchSAddr : ComplexPattern<iPTR, 2, "SelectScratchSAddr", [], [SDNPWantRoot], -10>;
15-
def ScratchSVAddr : ComplexPattern<iPTR, 3, "SelectScratchSVAddr", [], [SDNPWantRoot], -10>;
14+
def GlobalSAddr : ComplexPattern<iPTR, 3, "SelectGlobalSAddr", [], [], -10>;
15+
def ScratchSAddr : ComplexPattern<iPTR, 2, "SelectScratchSAddr", [], [], -10>;
16+
def ScratchSVAddr : ComplexPattern<iPTR, 3, "SelectScratchSVAddr", [], [], -10>;
17+
}
1618

1719
//===----------------------------------------------------------------------===//
1820
// FLAT classes

‎llvm/lib/Target/ARM/ARMInstrInfo.td‎

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1225,25 +1225,25 @@ def PostIdxRegShiftedAsmOperand : AsmOperandClass {
12251225
let ParserMethod = "parsePostIdxReg";
12261226
}
12271227
def am2offset_reg : MemOperand,
1228-
ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
1229-
[], [SDNPWantRoot]> {
1228+
ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg"> {
12301229
let EncoderMethod = "getAddrMode2OffsetOpValue";
12311230
let PrintMethod = "printAddrMode2OffsetOperand";
12321231
// When using this for assembly, it's always as a post-index offset.
12331232
let ParserMatchClass = PostIdxRegShiftedAsmOperand;
12341233
let MIOperandInfo = (ops GPRnopc, i32imm);
1234+
let WantsRoot = true;
12351235
}
12361236

12371237
// FIXME: am2offset_imm should only need the immediate, not the GPR. Having
12381238
// the GPR is purely vestigal at this point.
12391239
def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
12401240
def am2offset_imm : MemOperand,
1241-
ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
1242-
[], [SDNPWantRoot]> {
1241+
ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm"> {
12431242
let EncoderMethod = "getAddrMode2OffsetOpValue";
12441243
let PrintMethod = "printAddrMode2OffsetOperand";
12451244
let ParserMatchClass = AM2OffsetImmAsmOperand;
12461245
let MIOperandInfo = (ops GPRnopc, i32imm);
1246+
let WantsRoot = true;
12471247
}
12481248

12491249

@@ -1275,13 +1275,12 @@ def AM3OffsetAsmOperand : AsmOperandClass {
12751275
let Name = "AM3Offset";
12761276
let ParserMethod = "parseAM3Offset";
12771277
}
1278-
def am3offset : MemOperand,
1279-
ComplexPattern<i32, 2, "SelectAddrMode3Offset",
1280-
[], [SDNPWantRoot]> {
1278+
def am3offset : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode3Offset"> {
12811279
let EncoderMethod = "getAddrMode3OffsetOpValue";
12821280
let PrintMethod = "printAddrMode3OffsetOperand";
12831281
let ParserMatchClass = AM3OffsetAsmOperand;
12841282
let MIOperandInfo = (ops GPR, i32imm);
1283+
let WantsRoot = true;
12851284
}
12861285

12871286
// ldstm_mode := {ia, ib, da, db}
@@ -1328,40 +1327,39 @@ def addrmode5fp16 : AddrMode5FP16 {
13281327
// addrmode6 := reg with optional alignment
13291328
//
13301329
def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
1331-
def addrmode6 : MemOperand,
1332-
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1330+
def addrmode6 : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
13331331
let PrintMethod = "printAddrMode6Operand";
13341332
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
13351333
let EncoderMethod = "getAddrMode6AddressOpValue";
13361334
let DecoderMethod = "DecodeAddrMode6Operand";
13371335
let ParserMatchClass = AddrMode6AsmOperand;
1336+
let WantsParent = true;
13381337
}
13391338

1340-
def am6offset : MemOperand,
1341-
ComplexPattern<i32, 1, "SelectAddrMode6Offset",
1342-
[], [SDNPWantRoot]> {
1339+
def am6offset : MemOperand, ComplexPattern<i32, 1, "SelectAddrMode6Offset"> {
13431340
let PrintMethod = "printAddrMode6OffsetOperand";
13441341
let MIOperandInfo = (ops GPR);
13451342
let EncoderMethod = "getAddrMode6OffsetOpValue";
13461343
let DecoderMethod = "DecodeGPRRegisterClass";
1344+
let WantsRoot = true;
13471345
}
13481346

13491347
// Special version of addrmode6 to handle alignment encoding for VST1/VLD1
13501348
// (single element from one lane) for size 32.
1351-
def addrmode6oneL32 : MemOperand,
1352-
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1349+
def addrmode6oneL32 : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
13531350
let PrintMethod = "printAddrMode6Operand";
13541351
let MIOperandInfo = (ops GPR:$addr, i32imm);
13551352
let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1353+
let WantsParent = true;
13561354
}
13571355

13581356
// Base class for addrmode6 with specific alignment restrictions.
1359-
class AddrMode6Align : MemOperand,
1360-
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1357+
class AddrMode6Align : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
13611358
let PrintMethod = "printAddrMode6Operand";
13621359
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
13631360
let EncoderMethod = "getAddrMode6AddressOpValue";
13641361
let DecoderMethod = "DecodeAddrMode6Operand";
1362+
let WantsParent = true;
13651363
}
13661364

13671365
// Special version of addrmode6 to handle no allowed alignment encoding for
@@ -1432,22 +1430,23 @@ def addrmode6align64or128or256 : AddrMode6Align {
14321430

14331431
// Special version of addrmode6 to handle alignment encoding for VLD-dup
14341432
// instructions, specifically VLD4-dup.
1435-
def addrmode6dup : MemOperand,
1436-
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1433+
def addrmode6dup : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
14371434
let PrintMethod = "printAddrMode6Operand";
14381435
let MIOperandInfo = (ops GPR:$addr, i32imm);
14391436
let EncoderMethod = "getAddrMode6DupAddressOpValue";
14401437
// FIXME: This is close, but not quite right. The alignment specifier is
14411438
// different.
14421439
let ParserMatchClass = AddrMode6AsmOperand;
1440+
let WantsParent = true;
14431441
}
14441442

14451443
// Base class for addrmode6dup with specific alignment restrictions.
14461444
class AddrMode6DupAlign : MemOperand,
1447-
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1445+
ComplexPattern<i32, 2, "SelectAddrMode6"> {
14481446
let PrintMethod = "printAddrMode6Operand";
14491447
let MIOperandInfo = (ops GPR:$addr, i32imm);
14501448
let EncoderMethod = "getAddrMode6DupAddressOpValue";
1449+
let WantsParent = true;
14511450
}
14521451

14531452
// Special version of addrmode6 to handle no allowed alignment encoding for

‎llvm/lib/Target/ARM/ARMInstrMVE.td‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -184,15 +184,16 @@ def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
184184
def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
185185
def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
186186

187-
class t2am_imm7_offset<int shift> : MemOperand,
188-
ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">",
189-
[], [SDNPWantRoot]> {
187+
class t2am_imm7_offset<int shift>
188+
: MemOperand,
189+
ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">"> {
190190
// They are printed the same way as the imm8 version
191191
let PrintMethod = "printT2AddrModeImm8OffsetOperand";
192192
let ParserMatchClass =
193193
!cast<AsmOperandClass>("t2am_imm7shift"#shift#"OffsetAsmOperand");
194194
let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">";
195195
let DecoderMethod = "DecodeT2Imm7<"#shift#">";
196+
let WantsRoot = true;
196197
}
197198

198199
// Operands for gather/scatter loads of the form [Rbase, Qoffsets]

‎llvm/lib/Target/ARM/ARMInstrThumb.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,8 +287,8 @@ def t_addrmode_sp : MemOperand,
287287

288288
// Inspects parent to determine whether an or instruction can be implemented as
289289
// an add (i.e. whether we know overflow won't occur in the add).
290-
def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [],
291-
[SDNPWantParent]>;
290+
let WantsParent = true in
291+
def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr">;
292292

293293
// Pattern to exclude immediates from matching
294294
def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -267,11 +267,11 @@ def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
267267
}
268268

269269
def t2am_imm8_offset : MemOperand,
270-
ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
271-
[], [SDNPWantRoot]> {
270+
ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset"> {
272271
let PrintMethod = "printT2AddrModeImm8OffsetOperand";
273272
let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
274273
let DecoderMethod = "DecodeT2Imm8";
274+
let WantsRoot = true;
275275
}
276276

277277
// t2addrmode_imm8s4 := reg +/- (imm8 << 2)

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