Skip to content

Commit c4744e4

Browse files
nikicnikic
committed
[LSR] Regenerate test checks (NFC)
1 parent e818202 commit c4744e4

File tree

2 files changed

+59
-17
lines changed

2 files changed

+59
-17
lines changed

‎llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll‎

Lines changed: 55 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s
23

34
; Test for assert resulting from inconsistent isLegalAddressingMode
@@ -7,13 +8,36 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
78

89
%0 = type { i32, double, i32, float }
910

10-
; CHECK-LABEL: @lsr_crash_preserve_addrspace_unknown_type(
11-
; CHECK: %scevgep1 = getelementptr i8, ptr addrspace(3) %tmp, i32 8
12-
; CHECK: load double, ptr addrspace(3) %scevgep1
1311

14-
; CHECK: %scevgep = getelementptr i8, ptr addrspace(3) %tmp, i32 16
15-
; CHECK: %tmp14 = load i32, ptr addrspace(3) %scevgep
1612
define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type() #0 {
13+
; CHECK-LABEL: define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type(
14+
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
15+
; CHECK-NEXT: [[BB:.*]]:
16+
; CHECK-NEXT: br label %[[BB1:.*]]
17+
; CHECK: [[BB1]]:
18+
; CHECK-NEXT: [[TMP:%.*]] = phi ptr addrspace(3) [ undef, %[[BB]] ], [ [[TMP18:%.*]], %[[BB17:.*]] ]
19+
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 8
20+
; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr addrspace(3) [[SCEVGEP1]], align 8
21+
; CHECK-NEXT: br label %[[BB4:.*]]
22+
; CHECK: [[BB4]]:
23+
; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB5:.*]]
24+
; CHECK: [[BB5]]:
25+
; CHECK-NEXT: unreachable
26+
; CHECK: [[BB8]]:
27+
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) [[TMP]], align 4
28+
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 0, [[TMP10]]
29+
; CHECK-NEXT: br i1 [[TMP11]], label %[[BB12:.*]], label %[[BB17]]
30+
; CHECK: [[BB12]]:
31+
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 16
32+
; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) [[SCEVGEP]], align 4
33+
; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 0, [[TMP14]]
34+
; CHECK-NEXT: br i1 [[TMP15]], label %[[BB16:.*]], label %[[BB17]]
35+
; CHECK: [[BB16]]:
36+
; CHECK-NEXT: unreachable
37+
; CHECK: [[BB17]]:
38+
; CHECK-NEXT: [[TMP18]] = getelementptr inbounds [[TMP0:%.*]], ptr addrspace(3) [[TMP]], i64 2
39+
; CHECK-NEXT: br label %[[BB1]]
40+
;
1741
bb:
1842
br label %bb1
1943

@@ -48,15 +72,33 @@ bb17: ; preds = %bb12, %bb8
4872
br label %bb1
4973
}
5074

51-
; CHECK-LABEL: @lsr_crash_preserve_addrspace_unknown_type2(
52-
; CHECK: %idx = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j
53-
; CHECK: %idx1 = getelementptr inbounds i8, ptr addrspace(3) %array2, i32 %j
54-
; CHECK: %t = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j
55-
; CHECK: %n8 = load i8, ptr addrspace(5) %t, align 4
56-
; CHECK: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)
57-
; CHECK: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)
58-
; CHECK: call void @llvm.memset.p5.i64(ptr addrspace(5) %idx, i8 42, i64 42, i1 false)
5975
define void @lsr_crash_preserve_addrspace_unknown_type2(ptr addrspace(5) %array, ptr addrspace(3) %array2) {
76+
; CHECK-LABEL: define void @lsr_crash_preserve_addrspace_unknown_type2(
77+
; CHECK-SAME: ptr addrspace(5) [[ARRAY:%.*]], ptr addrspace(3) [[ARRAY2:%.*]]) {
78+
; CHECK-NEXT: [[ENTRY:.*]]:
79+
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
80+
; CHECK: [[FOR_BODY]]:
81+
; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_INC:.*]] ], [ 0, %[[ENTRY]] ]
82+
; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]
83+
; CHECK-NEXT: [[IDX1:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[ARRAY2]], i32 [[J]]
84+
; CHECK-NEXT: [[T:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]
85+
; CHECK-NEXT: [[N8:%.*]] = load i8, ptr addrspace(5) [[T]], align 4
86+
; CHECK-NEXT: [[N7:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[T]], i32 42
87+
; CHECK-NEXT: [[N9:%.*]] = load i8, ptr addrspace(5) [[N7]], align 4
88+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[J]], 42
89+
; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN17:.*]], label %[[FOR_INC]]
90+
; CHECK: [[IF_THEN17]]:
91+
; CHECK-NEXT: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)
92+
; CHECK-NEXT: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)
93+
; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[IDX]], i8 42, i64 42, i1 false)
94+
; CHECK-NEXT: br label %[[FOR_INC]]
95+
; CHECK: [[FOR_INC]]:
96+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i1 [[CMP]], true
97+
; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[J]], 1
98+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[END:.*]], label %[[FOR_BODY]]
99+
; CHECK: [[END]]:
100+
; CHECK-NEXT: ret void
101+
;
60102
entry:
61103
br label %for.body
62104

‎llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ target triple = "thumbv6m-arm-none-eabi"
1818

1919
; Test case 01: -1*reg is not free for the Thumb1 target.
2020
define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n) nounwind {
21-
; CHECK-LABEL: define ptr @negativeOneCase
22-
; CHECK-SAME: (ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
21+
; CHECK-LABEL: define ptr @negativeOneCase(
22+
; CHECK-SAME: ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2323
; CHECK-NEXT: entry:
2424
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 -1
2525
; CHECK-NEXT: br label [[WHILE_COND:%.*]]
@@ -85,8 +85,8 @@ while.end8: ; preds = %while.cond2
8585
; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for
8686
; the Thumb1 target.
8787
define void @negativeFourCase(ptr %ptr1, ptr %ptr2) nounwind {
88-
; CHECK-LABEL: define void @negativeFourCase
89-
; CHECK-SAME: (ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] {
88+
; CHECK-LABEL: define void @negativeFourCase(
89+
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] {
9090
; CHECK-NEXT: entry:
9191
; CHECK-NEXT: br label [[FOR_COND6_PREHEADER_US_I_I:%.*]]
9292
; CHECK: for.cond6.preheader.us.i.i:

0 commit comments

Comments
 (0)