@@ -1160,115 +1160,8 @@ u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
11601160 __v; \
11611161 })
11621162
1163- u64 vcpu_read_sys_reg (const struct kvm_vcpu * vcpu , int reg );
1164- void vcpu_write_sys_reg (struct kvm_vcpu * vcpu , u64 val , int reg );
1165-
1166- static inline bool __vcpu_read_sys_reg_from_cpu (int reg , u64 * val )
1167- {
1168- /*
1169- * *** VHE ONLY ***
1170- *
1171- * System registers listed in the switch are not saved on every
1172- * exit from the guest but are only saved on vcpu_put.
1173- *
1174- * SYSREGS_ON_CPU *MUST* be checked before using this helper.
1175- *
1176- * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1177- * should never be listed below, because the guest cannot modify its
1178- * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1179- * thread when emulating cross-VCPU communication.
1180- */
1181- if (!has_vhe ())
1182- return false;
1183-
1184- switch (reg ) {
1185- case SCTLR_EL1 : * val = read_sysreg_s (SYS_SCTLR_EL12 ); break ;
1186- case CPACR_EL1 : * val = read_sysreg_s (SYS_CPACR_EL12 ); break ;
1187- case TTBR0_EL1 : * val = read_sysreg_s (SYS_TTBR0_EL12 ); break ;
1188- case TTBR1_EL1 : * val = read_sysreg_s (SYS_TTBR1_EL12 ); break ;
1189- case TCR_EL1 : * val = read_sysreg_s (SYS_TCR_EL12 ); break ;
1190- case TCR2_EL1 : * val = read_sysreg_s (SYS_TCR2_EL12 ); break ;
1191- case PIR_EL1 : * val = read_sysreg_s (SYS_PIR_EL12 ); break ;
1192- case PIRE0_EL1 : * val = read_sysreg_s (SYS_PIRE0_EL12 ); break ;
1193- case POR_EL1 : * val = read_sysreg_s (SYS_POR_EL12 ); break ;
1194- case ESR_EL1 : * val = read_sysreg_s (SYS_ESR_EL12 ); break ;
1195- case AFSR0_EL1 : * val = read_sysreg_s (SYS_AFSR0_EL12 ); break ;
1196- case AFSR1_EL1 : * val = read_sysreg_s (SYS_AFSR1_EL12 ); break ;
1197- case FAR_EL1 : * val = read_sysreg_s (SYS_FAR_EL12 ); break ;
1198- case MAIR_EL1 : * val = read_sysreg_s (SYS_MAIR_EL12 ); break ;
1199- case VBAR_EL1 : * val = read_sysreg_s (SYS_VBAR_EL12 ); break ;
1200- case CONTEXTIDR_EL1 : * val = read_sysreg_s (SYS_CONTEXTIDR_EL12 );break ;
1201- case TPIDR_EL0 : * val = read_sysreg_s (SYS_TPIDR_EL0 ); break ;
1202- case TPIDRRO_EL0 : * val = read_sysreg_s (SYS_TPIDRRO_EL0 ); break ;
1203- case TPIDR_EL1 : * val = read_sysreg_s (SYS_TPIDR_EL1 ); break ;
1204- case AMAIR_EL1 : * val = read_sysreg_s (SYS_AMAIR_EL12 ); break ;
1205- case CNTKCTL_EL1 : * val = read_sysreg_s (SYS_CNTKCTL_EL12 ); break ;
1206- case ELR_EL1 : * val = read_sysreg_s (SYS_ELR_EL12 ); break ;
1207- case SPSR_EL1 : * val = read_sysreg_s (SYS_SPSR_EL12 ); break ;
1208- case PAR_EL1 : * val = read_sysreg_par (); break ;
1209- case DACR32_EL2 : * val = read_sysreg_s (SYS_DACR32_EL2 ); break ;
1210- case IFSR32_EL2 : * val = read_sysreg_s (SYS_IFSR32_EL2 ); break ;
1211- case DBGVCR32_EL2 : * val = read_sysreg_s (SYS_DBGVCR32_EL2 ); break ;
1212- case ZCR_EL1 : * val = read_sysreg_s (SYS_ZCR_EL12 ); break ;
1213- case SCTLR2_EL1 : * val = read_sysreg_s (SYS_SCTLR2_EL12 ); break ;
1214- default : return false;
1215- }
1216-
1217- return true;
1218- }
1219-
1220- static inline bool __vcpu_write_sys_reg_to_cpu (u64 val , int reg )
1221- {
1222- /*
1223- * *** VHE ONLY ***
1224- *
1225- * System registers listed in the switch are not restored on every
1226- * entry to the guest but are only restored on vcpu_load.
1227- *
1228- * SYSREGS_ON_CPU *MUST* be checked before using this helper.
1229- *
1230- * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1231- * should never be listed below, because the MPIDR should only be set
1232- * once, before running the VCPU, and never changed later.
1233- */
1234- if (!has_vhe ())
1235- return false;
1236-
1237- switch (reg ) {
1238- case SCTLR_EL1 : write_sysreg_s (val , SYS_SCTLR_EL12 ); break ;
1239- case CPACR_EL1 : write_sysreg_s (val , SYS_CPACR_EL12 ); break ;
1240- case TTBR0_EL1 : write_sysreg_s (val , SYS_TTBR0_EL12 ); break ;
1241- case TTBR1_EL1 : write_sysreg_s (val , SYS_TTBR1_EL12 ); break ;
1242- case TCR_EL1 : write_sysreg_s (val , SYS_TCR_EL12 ); break ;
1243- case TCR2_EL1 : write_sysreg_s (val , SYS_TCR2_EL12 ); break ;
1244- case PIR_EL1 : write_sysreg_s (val , SYS_PIR_EL12 ); break ;
1245- case PIRE0_EL1 : write_sysreg_s (val , SYS_PIRE0_EL12 ); break ;
1246- case POR_EL1 : write_sysreg_s (val , SYS_POR_EL12 ); break ;
1247- case ESR_EL1 : write_sysreg_s (val , SYS_ESR_EL12 ); break ;
1248- case AFSR0_EL1 : write_sysreg_s (val , SYS_AFSR0_EL12 ); break ;
1249- case AFSR1_EL1 : write_sysreg_s (val , SYS_AFSR1_EL12 ); break ;
1250- case FAR_EL1 : write_sysreg_s (val , SYS_FAR_EL12 ); break ;
1251- case MAIR_EL1 : write_sysreg_s (val , SYS_MAIR_EL12 ); break ;
1252- case VBAR_EL1 : write_sysreg_s (val , SYS_VBAR_EL12 ); break ;
1253- case CONTEXTIDR_EL1 : write_sysreg_s (val , SYS_CONTEXTIDR_EL12 );break ;
1254- case TPIDR_EL0 : write_sysreg_s (val , SYS_TPIDR_EL0 ); break ;
1255- case TPIDRRO_EL0 : write_sysreg_s (val , SYS_TPIDRRO_EL0 ); break ;
1256- case TPIDR_EL1 : write_sysreg_s (val , SYS_TPIDR_EL1 ); break ;
1257- case AMAIR_EL1 : write_sysreg_s (val , SYS_AMAIR_EL12 ); break ;
1258- case CNTKCTL_EL1 : write_sysreg_s (val , SYS_CNTKCTL_EL12 ); break ;
1259- case ELR_EL1 : write_sysreg_s (val , SYS_ELR_EL12 ); break ;
1260- case SPSR_EL1 : write_sysreg_s (val , SYS_SPSR_EL12 ); break ;
1261- case PAR_EL1 : write_sysreg_s (val , SYS_PAR_EL1 ); break ;
1262- case DACR32_EL2 : write_sysreg_s (val , SYS_DACR32_EL2 ); break ;
1263- case IFSR32_EL2 : write_sysreg_s (val , SYS_IFSR32_EL2 ); break ;
1264- case DBGVCR32_EL2 : write_sysreg_s (val , SYS_DBGVCR32_EL2 ); break ;
1265- case ZCR_EL1 : write_sysreg_s (val , SYS_ZCR_EL12 ); break ;
1266- case SCTLR2_EL1 : write_sysreg_s (val , SYS_SCTLR2_EL12 ); break ;
1267- default : return false;
1268- }
1269-
1270- return true;
1271- }
1163+ u64 vcpu_read_sys_reg (const struct kvm_vcpu * , enum vcpu_sysreg );
1164+ void vcpu_write_sys_reg (struct kvm_vcpu * , u64 , enum vcpu_sysreg );
12721165
12731166struct kvm_vm_stat {
12741167 struct kvm_vm_stat_generic generic ;
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