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torvaldstorvalds
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Merge tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull generic phy driver fixes from Vinod Koul: - Qualcomm repeater override properties, qmp pcie bindings fix for clocks and initialization sequence for firmware power down case - Marvell comphy bindings clock and child node constraints - Tegra xusb device reference leaks fix - TI omap usb device ref leak on unbind and RGMII IS settings fix * tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmware phy: ti: gmii-sel: Always write the RGMII ID setting dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings phy: ti-pipe3: fix device leak at unbind phy: ti: omap-usb2: fix device leak at unbind phy: tegra: xusb: fix device and OF node leak at probe dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints phy: qualcomm: phy-qcom-eusb2-repeater: fix override properties
2 parents 0676181 + 6cb8c1f commit 79e8447

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8 files changed

+114
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‎Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml‎

Lines changed: 21 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -47,32 +47,34 @@ properties:
4747
const: 0
4848

4949
clocks:
50+
minItems: 1
5051
maxItems: 3
51-
description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
5252

5353
clock-names:
54-
items:
55-
- const: mg_clk
56-
- const: mg_core_clk
57-
- const: axi_clk
54+
minItems: 1
55+
maxItems: 3
5856

5957
marvell,system-controller:
6058
description: Phandle to the Marvell system controller (CP110 only)
6159
$ref: /schemas/types.yaml#/definitions/phandle
6260

6361
patternProperties:
64-
'^phy@[0-2]$':
62+
'^phy@[0-5]$':
6563
description: A COMPHY lane child node
6664
type: object
6765
additionalProperties: false
6866

6967
properties:
7068
reg:
7169
description: COMPHY lane number
70+
maximum: 5
7271

7372
'#phy-cells':
7473
const: 1
7574

75+
connector:
76+
type: object
77+
7678
required:
7779
- reg
7880
- '#phy-cells'
@@ -91,13 +93,24 @@ allOf:
9193

9294
then:
9395
properties:
94-
clocks: false
95-
clock-names: false
96+
clocks:
97+
maxItems: 1
98+
clock-names:
99+
const: xtal
96100

97101
required:
98102
- reg-names
99103

100104
else:
105+
properties:
106+
clocks:
107+
minItems: 3
108+
clock-names:
109+
items:
110+
- const: mg_clk
111+
- const: mg_core_clk
112+
- const: axi_clk
113+
101114
required:
102115
- marvell,system-controller
103116

‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,8 @@ allOf:
176176
compatible:
177177
contains:
178178
enum:
179+
- qcom,sa8775p-qmp-gen4x2-pcie-phy
180+
- qcom,sa8775p-qmp-gen4x4-pcie-phy
179181
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
180182
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
181183
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
@@ -197,8 +199,6 @@ allOf:
197199
contains:
198200
enum:
199201
- qcom,qcs8300-qmp-gen4x2-pcie-phy
200-
- qcom,sa8775p-qmp-gen4x2-pcie-phy
201-
- qcom,sa8775p-qmp-gen4x4-pcie-phy
202202
then:
203203
properties:
204204
clocks:

‎drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,13 +127,13 @@ static int eusb2_repeater_init(struct phy *phy)
127127
rptr->cfg->init_tbl[i].value);
128128

129129
/* Override registers from devicetree values */
130-
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val))
130+
if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val))
131131
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val);
132132

133133
if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val))
134134
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val);
135135

136-
if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val))
136+
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val))
137137
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val);
138138

139139
/* Wait for status OK */

‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3067,6 +3067,14 @@ struct qmp_pcie {
30673067
struct clk_fixed_rate aux_clk_fixed;
30683068
};
30693069

3070+
static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
3071+
{
3072+
u32 reg;
3073+
3074+
reg = readl(base + offset);
3075+
return (reg & val) == val;
3076+
}
3077+
30703078
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
30713079
{
30723080
u32 reg;
@@ -4339,16 +4347,21 @@ static int qmp_pcie_init(struct phy *phy)
43394347
struct qmp_pcie *qmp = phy_get_drvdata(phy);
43404348
const struct qmp_phy_cfg *cfg = qmp->cfg;
43414349
void __iomem *pcs = qmp->pcs;
4342-
bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
43434350
int ret;
43444351

4345-
qmp->skip_init = qmp->nocsr_reset && phy_initialized;
43464352
/*
4347-
* We need to check the existence of init sequences in two cases:
4348-
* 1. The PHY doesn't support no_csr reset.
4349-
* 2. The PHY supports no_csr reset but isn't initialized by bootloader.
4350-
* As we can't skip init in these two cases.
4353+
* We can skip PHY initialization if all of the following conditions
4354+
* are met:
4355+
* 1. The PHY supports the nocsr_reset that preserves the PHY config.
4356+
* 2. The PHY was started (and not powered down again) by the
4357+
* bootloader, with all of the expected bits set correctly.
4358+
* In this case, we can continue without having the init sequence
4359+
* defined in the driver.
43514360
*/
4361+
qmp->skip_init = qmp->nocsr_reset &&
4362+
qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) &&
4363+
qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl);
4364+
43524365
if (!qmp->skip_init && !cfg->tbls.serdes_num) {
43534366
dev_err(qmp->dev, "Init sequence not available\n");
43544367
return -ENODATA;

‎drivers/phy/tegra/xusb-tegra210.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3164,18 +3164,22 @@ tegra210_xusb_padctl_probe(struct device *dev,
31643164
}
31653165

31663166
pdev = of_find_device_by_node(np);
3167+
of_node_put(np);
31673168
if (!pdev) {
31683169
dev_warn(dev, "PMC device is not available\n");
31693170
goto out;
31703171
}
31713172

3172-
if (!platform_get_drvdata(pdev))
3173+
if (!platform_get_drvdata(pdev)) {
3174+
put_device(&pdev->dev);
31733175
return ERR_PTR(-EPROBE_DEFER);
3176+
}
31743177

31753178
padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk");
31763179
if (!padctl->regmap)
31773180
dev_info(dev, "failed to find PMC regmap\n");
31783181

3182+
put_device(&pdev->dev);
31793183
out:
31803184
return &padctl->base;
31813185
}

‎drivers/phy/ti/phy-gmii-sel.c‎

Lines changed: 39 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ enum {
3434
PHY_GMII_SEL_PORT_MODE = 0,
3535
PHY_GMII_SEL_RGMII_ID_MODE,
3636
PHY_GMII_SEL_RMII_IO_CLK_EN,
37+
PHY_GMII_SEL_FIXED_TX_DELAY,
3738
PHY_GMII_SEL_LAST,
3839
};
3940

@@ -127,6 +128,11 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
127128
goto unsupported;
128129
}
129130

131+
/* With a fixed delay, some modes are not supported at all. */
132+
if (soc_data->features & BIT(PHY_GMII_SEL_FIXED_TX_DELAY) &&
133+
rgmii_id != 0)
134+
return -EINVAL;
135+
130136
if_phy->phy_if_mode = submode;
131137

132138
dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
@@ -210,25 +216,46 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
210216

211217
static const
212218
struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
213-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
214-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
215-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
216-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
217-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
218-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
219-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
220-
{ [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
219+
{
220+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
221+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4),
222+
}, {
223+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
224+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4),
225+
}, {
226+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
227+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4),
228+
}, {
229+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
230+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4),
231+
}, {
232+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
233+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4),
234+
}, {
235+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
236+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4),
237+
}, {
238+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
239+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4),
240+
}, {
241+
[PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
242+
[PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4),
243+
},
221244
};
222245

223246
static const
224247
struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
225248
.use_of_data = true,
249+
.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
250+
BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
226251
.regfields = phy_gmii_sel_fields_am654,
227252
};
228253

229254
static const
230255
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
231256
.use_of_data = true,
257+
.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
258+
BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
232259
.regfields = phy_gmii_sel_fields_am654,
233260
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
234261
BIT(PHY_INTERFACE_MODE_USXGMII),
@@ -239,6 +266,8 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
239266
static const
240267
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
241268
.use_of_data = true,
269+
.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
270+
BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
242271
.regfields = phy_gmii_sel_fields_am654,
243272
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
244273
.num_ports = 8,
@@ -248,6 +277,8 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
248277
static const
249278
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
250279
.use_of_data = true,
280+
.features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
281+
BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
251282
.regfields = phy_gmii_sel_fields_am654,
252283
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
253284
BIT(PHY_INTERFACE_MODE_USXGMII),

‎drivers/phy/ti/phy-omap-usb2.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,13 @@ static void omap_usb2_init_errata(struct omap_usb *phy)
363363
phy->flags |= OMAP_USB2_DISABLE_CHRG_DET;
364364
}
365365

366+
static void omap_usb2_put_device(void *_dev)
367+
{
368+
struct device *dev = _dev;
369+
370+
put_device(dev);
371+
}
372+
366373
static int omap_usb2_probe(struct platform_device *pdev)
367374
{
368375
struct omap_usb *phy;
@@ -373,6 +380,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
373380
struct device_node *control_node;
374381
struct platform_device *control_pdev;
375382
const struct usb_phy_data *phy_data;
383+
int ret;
376384

377385
phy_data = device_get_match_data(&pdev->dev);
378386
if (!phy_data)
@@ -423,6 +431,11 @@ static int omap_usb2_probe(struct platform_device *pdev)
423431
return -EINVAL;
424432
}
425433
phy->control_dev = &control_pdev->dev;
434+
435+
ret = devm_add_action_or_reset(&pdev->dev, omap_usb2_put_device,
436+
phy->control_dev);
437+
if (ret)
438+
return ret;
426439
} else {
427440
if (of_property_read_u32_index(node,
428441
"syscon-phy-power", 1,

‎drivers/phy/ti/phy-ti-pipe3.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -667,12 +667,20 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
667667
return 0;
668668
}
669669

670+
static void ti_pipe3_put_device(void *_dev)
671+
{
672+
struct device *dev = _dev;
673+
674+
put_device(dev);
675+
}
676+
670677
static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
671678
{
672679
struct device *dev = phy->dev;
673680
struct device_node *node = dev->of_node;
674681
struct device_node *control_node;
675682
struct platform_device *control_pdev;
683+
int ret;
676684

677685
phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
678686
"syscon-phy-power");
@@ -704,6 +712,11 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
704712
}
705713

706714
phy->control_dev = &control_pdev->dev;
715+
716+
ret = devm_add_action_or_reset(dev, ti_pipe3_put_device,
717+
phy->control_dev);
718+
if (ret)
719+
return ret;
707720
}
708721

709722
if (phy->mode == PIPE3_MODE_PCIE) {

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