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victorlu-amdalexdeucher
victorlu-amd
authored and
alexdeucher
committed
drm/amdgpu: Use correct KIQ MEC engine for gfx9.4.3 (v5)
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0. Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC and amdgpu_device_xcc_wreg/rreg to use the new xcc_id parameter. Using amdgpu_sriov_runtime to determine whether to access via kiq or RLC is sufficient for now. v5: add condition in amdgpu_device_xcc_w/rreg, remove trace func call v4: avoid using amdgpu_sriov_w/rreg v3: use W/RREG32_XCC to handle non-kiq case v2: define amdgpu_device_xcc_wreg/rreg instead of changing parameters of amdgpu_device_wreg/rreg Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-18
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9 files changed

+116
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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1159,11 +1159,18 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
11591159
uint32_t reg, uint32_t acc_flags);
11601160
u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
11611161
u64 reg_addr);
1162+
uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1163+
uint32_t reg, uint32_t acc_flags,
1164+
uint32_t xcc_id);
11621165
void amdgpu_device_wreg(struct amdgpu_device *adev,
11631166
uint32_t reg, uint32_t v,
11641167
uint32_t acc_flags);
11651168
void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
11661169
u64 reg_addr, u32 reg_data);
1170+
void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1171+
uint32_t reg, uint32_t v,
1172+
uint32_t acc_flags,
1173+
uint32_t xcc_id);
11671174
void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
11681175
uint32_t reg, uint32_t v, uint32_t xcc_id);
11691176
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
@@ -1204,8 +1211,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12041211
#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
12051212
#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
12061213

1207-
#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1208-
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1214+
#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1215+
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
12091216

12101217
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
12111218
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
@@ -1215,6 +1222,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
12151222
#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
12161223
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
12171224
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1225+
#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1226+
#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
12181227
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
12191228
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
12201229
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd,
300300
hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI);
301301

302302
for (reg = hqd_base; reg <= hqd_end; reg++)
303-
WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
303+
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
304304

305305

306306
/* Activate doorbell logic before triggering WPTR poll. */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
239239

240240
for (reg = hqd_base;
241241
reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)
242-
WREG32_RLC(reg, mqd_hqd[reg - hqd_base]);
242+
WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst);
243243

244244

245245
/* Activate doorbell logic before triggering WPTR poll. */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 87 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@
7373
#include "amdgpu_pmu.h"
7474
#include "amdgpu_fru_eeprom.h"
7575
#include "amdgpu_reset.h"
76+
#include "amdgpu_virt.h"
7677

7778
#include <linux/suspend.h>
7879
#include <drm/task_barrier.h>
@@ -472,7 +473,7 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
472473
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
473474
amdgpu_sriov_runtime(adev) &&
474475
down_read_trylock(&adev->reset_domain->sem)) {
475-
ret = amdgpu_kiq_rreg(adev, reg);
476+
ret = amdgpu_kiq_rreg(adev, reg, 0);
476477
up_read(&adev->reset_domain->sem);
477478
} else {
478479
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
@@ -509,6 +510,49 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
509510
BUG();
510511
}
511512

513+
514+
/**
515+
* amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
516+
*
517+
* @adev: amdgpu_device pointer
518+
* @reg: dword aligned register offset
519+
* @acc_flags: access flags which require special behavior
520+
* @xcc_id: xcc accelerated compute core id
521+
*
522+
* Returns the 32 bit value from the offset specified.
523+
*/
524+
uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
525+
uint32_t reg, uint32_t acc_flags,
526+
uint32_t xcc_id)
527+
{
528+
uint32_t ret, rlcg_flag;
529+
530+
if (amdgpu_device_skip_hw_access(adev))
531+
return 0;
532+
533+
if ((reg * 4) < adev->rmmio_size) {
534+
if (amdgpu_sriov_vf(adev) &&
535+
!amdgpu_sriov_runtime(adev) &&
536+
adev->gfx.rlc.rlcg_reg_access_supported &&
537+
amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
538+
GC_HWIP, false,
539+
&rlcg_flag)) {
540+
ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
541+
} else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
542+
amdgpu_sriov_runtime(adev) &&
543+
down_read_trylock(&adev->reset_domain->sem)) {
544+
ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
545+
up_read(&adev->reset_domain->sem);
546+
} else {
547+
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
548+
}
549+
} else {
550+
ret = adev->pcie_rreg(adev, reg * 4);
551+
}
552+
553+
return ret;
554+
}
555+
512556
/*
513557
* MMIO register write with bytes helper functions
514558
* @offset:bytes offset from MMIO start
@@ -556,7 +600,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
556600
if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
557601
amdgpu_sriov_runtime(adev) &&
558602
down_read_trylock(&adev->reset_domain->sem)) {
559-
amdgpu_kiq_wreg(adev, reg, v);
603+
amdgpu_kiq_wreg(adev, reg, v, 0);
560604
up_read(&adev->reset_domain->sem);
561605
} else {
562606
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
@@ -597,6 +641,47 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
597641
}
598642
}
599643

644+
/**
645+
* amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
646+
*
647+
* @adev: amdgpu_device pointer
648+
* @reg: dword aligned register offset
649+
* @v: 32 bit value to write to the register
650+
* @acc_flags: access flags which require special behavior
651+
* @xcc_id: xcc accelerated compute core id
652+
*
653+
* Writes the value specified to the offset specified.
654+
*/
655+
void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
656+
uint32_t reg, uint32_t v,
657+
uint32_t acc_flags, uint32_t xcc_id)
658+
{
659+
uint32_t rlcg_flag;
660+
661+
if (amdgpu_device_skip_hw_access(adev))
662+
return;
663+
664+
if ((reg * 4) < adev->rmmio_size) {
665+
if (amdgpu_sriov_vf(adev) &&
666+
!amdgpu_sriov_runtime(adev) &&
667+
adev->gfx.rlc.rlcg_reg_access_supported &&
668+
amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
669+
GC_HWIP, true,
670+
&rlcg_flag)) {
671+
amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
672+
} else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
673+
amdgpu_sriov_runtime(adev) &&
674+
down_read_trylock(&adev->reset_domain->sem)) {
675+
amdgpu_kiq_wreg(adev, reg, v, xcc_id);
676+
up_read(&adev->reset_domain->sem);
677+
} else {
678+
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
679+
}
680+
} else {
681+
adev->pcie_wreg(adev, reg * 4, v);
682+
}
683+
}
684+
600685
/**
601686
* amdgpu_device_indirect_rreg - read an indirect register
602687
*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -931,12 +931,12 @@ void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
931931
func(adev, ras_error_status, i);
932932
}
933933

934-
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
934+
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id)
935935
{
936936
signed long r, cnt = 0;
937937
unsigned long flags;
938938
uint32_t seq, reg_val_offs = 0, value = 0;
939-
struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
939+
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
940940
struct amdgpu_ring *ring = &kiq->ring;
941941

942942
if (amdgpu_device_skip_hw_access(adev))
@@ -999,12 +999,12 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
999999
return ~0;
10001000
}
10011001

1002-
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1002+
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id)
10031003
{
10041004
signed long r, cnt = 0;
10051005
unsigned long flags;
10061006
uint32_t seq;
1007-
struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1007+
struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
10081008
struct amdgpu_ring *ring = &kiq->ring;
10091009

10101010
BUG_ON(!ring->funcs->emit_wreg);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -521,8 +521,8 @@ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
521521
int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
522522
struct amdgpu_irq_src *source,
523523
struct amdgpu_iv_entry *entry);
524-
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
525-
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
524+
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id);
525+
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
526526
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
527527
void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
528528

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -943,7 +943,7 @@ void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
943943
}
944944
}
945945

946-
static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
946+
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
947947
u32 acc_flags, u32 hwip,
948948
bool write, u32 *rlcg_flag)
949949
{
@@ -976,7 +976,7 @@ static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
976976
return ret;
977977
}
978978

979-
static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
979+
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
980980
{
981981
struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
982982
uint32_t timeout = 50000;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -367,4 +367,8 @@ bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
367367
uint32_t ucode_id);
368368
void amdgpu_virt_post_reset(struct amdgpu_device *adev);
369369
bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
370+
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
371+
u32 acc_flags, u32 hwip,
372+
bool write, u32 *rlcg_flag);
373+
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
370374
#endif

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2739,16 +2739,16 @@ static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
27392739

27402740
switch (state) {
27412741
case AMDGPU_IRQ_STATE_DISABLE:
2742-
mec_int_cntl = RREG32(mec_int_cntl_reg);
2742+
mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
27432743
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
27442744
TIME_STAMP_INT_ENABLE, 0);
2745-
WREG32(mec_int_cntl_reg, mec_int_cntl);
2745+
WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
27462746
break;
27472747
case AMDGPU_IRQ_STATE_ENABLE:
2748-
mec_int_cntl = RREG32(mec_int_cntl_reg);
2748+
mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
27492749
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
27502750
TIME_STAMP_INT_ENABLE, 1);
2751-
WREG32(mec_int_cntl_reg, mec_int_cntl);
2751+
WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
27522752
break;
27532753
default:
27542754
break;

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