|
28 | 28 | #define PCI_GLI_9750_PM_CTRL 0xFC
|
29 | 29 | #define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
|
30 | 30 |
|
| 31 | +#define PCI_GLI_9750_CORRERR_MASK 0x214 |
| 32 | +#define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) |
| 33 | + |
31 | 34 | #define SDHCI_GLI_9750_CFG2 0x848
|
32 | 35 | #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
|
33 | 36 | #define GLI_9750_CFG2_L1DLY_VALUE 0x1F
|
|
152 | 155 | #define PCI_GLI_9755_PM_CTRL 0xFC
|
153 | 156 | #define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
|
154 | 157 |
|
| 158 | +#define PCI_GLI_9755_CORRERR_MASK 0x214 |
| 159 | +#define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) |
| 160 | + |
155 | 161 | #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
|
156 | 162 | #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
|
157 | 163 |
|
@@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host)
|
561 | 567 | value &= ~PCI_GLI_9750_PM_STATE;
|
562 | 568 | pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
|
563 | 569 |
|
| 570 | + /* mask the replay timer timeout of AER */ |
| 571 | + pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value); |
| 572 | + value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; |
| 573 | + pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value); |
| 574 | + |
564 | 575 | gl9750_wt_off(host);
|
565 | 576 | }
|
566 | 577 |
|
@@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
|
770 | 781 | value &= ~PCI_GLI_9755_PM_STATE;
|
771 | 782 | pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
|
772 | 783 |
|
| 784 | + /* mask the replay timer timeout of AER */ |
| 785 | + pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value); |
| 786 | + value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; |
| 787 | + pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value); |
| 788 | + |
773 | 789 | gl9755_wt_off(pdev);
|
774 | 790 | }
|
775 | 791 |
|
|
0 commit comments