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2 parents a375894 + b59ee02 commit 00722fbCopy full SHA for 00722fb
flow/designs/rapidus2hp/cva6/config.mk
@@ -102,7 +102,7 @@ ifeq ($(SYNTH_HDL_FRONTEND),verific)
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else
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# Reduce the amount of resizing done between GPL and DPL
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export EARLY_SIZING_CAP_RATIO = 6
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- ifeq ($(TRACK_OPTION),6T)
+ ifeq ($(PLACE_SITE),SC6T)
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# Decrease the utilization so that the tall macros fit
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export CORE_UTILIZATION = 50
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flow/designs/rapidus2hp/hercules_is_int/config.mk
@@ -22,7 +22,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects
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export SYNTH_HDL_FRONTEND = slang
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export SYNTH_HIERARCHICAL ?= 0
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-ifeq ($(TRACK_OPTION), 6T)
+ifeq ($(PLACE_SITE), SC6T)
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export CORE_UTILIZATION = 30
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export CORE_UTILIZATION = 35
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