Merge pull request The-OpenROAD-Project#3413 from The-OpenROAD-Project-staging/is_int-config-cleanup

hercules_is_int config cleanup

Author: maliberty

flow/designs/rapidus2hp/hercules_is_int/config.mk

@@ -5,39 +5,60 @@ export DESIGN_NAME            = hercules_is_int
 export SRC_HOME = /platforms/Rapidus/designs/hercules_is_int
 
 ifeq ($(FLOW_VARIANT), gatelevel)
-  export SYNTH_NETLIST_FILES = $(SRC_HOME)/ca78_8t_postroute_0707.v
+  export SYNTH_NETLIST_FILES  = $(SRC_HOME)/ca78_8t_postroute_0707.v
 endif
 
-export VERILOG_FILES          =	$(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \
+export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/hercules_issue/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/shared/verilog/*.sv)) \
 	$(sort $(wildcard $(SRC_HOME)/models/cells/generic/*.sv))
 
-export VERILOG_INCLUDE_DIRS =  $(SRC_HOME)/hercules_issue/verilog \
+export VERILOG_INCLUDE_DIRS   = $(SRC_HOME)/hercules_issue/verilog \
 	$(SRC_HOME)/shared/verilog \
 	$(SRC_HOME)/models/cells/generic
 
-export VERILOG_DEFINES +=
-
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/prects.sdc
 
 # Must be defined before the ifeq's
-export SYNTH_HDL_FRONTEND  = slang
-export SYNTH_HIERARCHICAL ?= 0
+export SYNTH_HDL_FRONTEND    ?= slang
+export SYNTH_HIERARCHICAL    ?= 0
 
 ifeq ($(PLACE_SITE), SC6T)
-  export CORE_UTILIZATION       = 30
+  export CORE_UTILIZATION     = 30
 else
-  export CORE_UTILIZATION       = 35
+  export CORE_UTILIZATION     = 35
 endif
 
-export CORE_MARGIN            = 2
-export MACRO_PLACE_HALO       = 2 2
-
+export CORE_MARGIN            = 1
 export PLACE_DENSITY          = 0.58
 
 # a smoketest for this option, there are a
 # few last gasp iterations
 export SKIP_LAST_GASP ?= 1
 
-# For use with SYNTH_HIERARCHICAL
-export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
+# Selectively keep module hierarchies to match baseline data
+# ifeq ($(SYNTH_HDL_FRONTEND), verific)
+#   export SYNTH_KEEP_MODULES = \hercules_is_grbt \
+# 	 \hercules_is_grf \
+# 	 \hercules_is_lsq \
+# 	 \hercules_is_lsq2 \
+# 	 \hercules_is_mx0(HERCULES_IQ_DATA_GATING=0)\
+# 	 \hercules_is_mx1(HERCULES_IQ_DATA_GATING=0) \
+# 	 \hercules_is_pcrf \
+# 	 \hercules_is_resc_ix \
+# 	 \hercules_is_resc_ls \
+# 	 \hercules_is_sxq
+# else
+#   export SYNTH_KEEP_MODULES = \hercules_is_grbt$$hercules_is_int.u_grbt \
+# 	\\hercules_is_grf$$hercules_is_int.u_grf \
+# 	\\hercules_is_lsq$$hercules_is_int.u_ls0_iq \
+# 	\\hercules_is_lsq$$hercules_is_int.u_ls1_iq \
+# 	\\hercules_is_lsq2$$hercules_is_int.u_ls2_iq \
+# 	\\hercules_is_mx0$$hercules_is_int.u_mx0_iq \
+# 	\\hercules_is_mx1$$hercules_is_int.u_mx1_iq \
+# 	\\hercules_is_pcrf$$hercules_is_int.u_pcrf \
+# 	\\hercules_is_resc_ix$$hercules_is_int.u_grcx \
+# 	\\hercules_is_resc_ls$$hercules_is_int.u_grcl \
+# 	\\hercules_is_sxq$$hercules_is_int.u_sx0_iq \
+# 	\\hercules_is_sxq$$hercules_is_int.u_sx1_iq
+#   endif
+# endif