Merge pull request The-OpenROAD-Project#3473 from The-OpenROAD-Project-staging/rtl-demo-sept-2025

added RTL demo files

Author: maliberty

flow/designs/rapidus2hp/cva6/autotuner_freq.json

@@ -0,0 +1,11 @@
+{
+    "_SDC_FILE_PATH": "constraint.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            1270,
+            1370
+        ],
+        "step": 0
+    }
+}

flow/designs/rapidus2hp/cva6/autotuner_phys.json

@@ -0,0 +1,74 @@
+{
+    "_SDC_FILE_PATH": "constraint.sdc",
+    "_SDC_CLK_PERIOD": {
+        "type": "float",
+        "minmax": [
+            1297.0415261866478,
+	    1297.0415261866478
+        ],
+        "step": 0
+    },
+    "CORE_UTILIZATION": {
+        "type": "int",
+        "minmax": [
+            40,
+            60
+        ],
+        "step": 1
+    },
+    "CTS_BUF_DISTANCE": {
+        "type": "int",
+        "minmax": [
+            25,
+            50
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_SIZE": {
+        "type": "int",
+        "minmax": [
+            30,
+            60
+        ],
+        "step": 1
+    },
+    "CTS_CLUSTER_DIAMETER": {
+        "type": "int",
+        "minmax": [
+            15,
+            25
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
+        "type": "int",
+        "minmax": [
+            0,
+            3
+        ],
+        "step": 1
+    },
+    "PLACE_SITE": {
+        "type": "string",
+        "values": [
+            "SC6T",
+            "SC8T"
+        ]
+    },
+    "CORE_MARGIN": {
+        "type": "float",
+        "minmax": [
+            0.75,
+            1.5
+        ],
+        "step": 0
+    }
+}

flow/designs/rapidus2hp/cva6/constraint_demo.sdc

@@ -0,0 +1,9 @@
+# Derived from cva6_synth.tcl and Makefiles
+
+set clk_name main_clk
+set clk_port clk_i
+set clk_ports_list [list $clk_port]
+set clk_period 1380
+set input_delay 0.46
+set output_delay 0.11
+create_clock [get_ports $clk_port] -name $clk_name -period $clk_period