Merge pull request The-OpenROAD-Project#3401 from The-OpenROAD-Project-staging/tighten-2508

maliberty · web-flow · commit 708458750afc · 2025-08-19T11:47:31.000Z
Tighten constraints for asap7, sky130hs designs
diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 475
+set clk_period 450
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 400
+set clk_period 380
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 400
+set clk_period 380
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 400
+set clk_period 360
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc
@@ -3,7 +3,7 @@
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1200
+set clk_period 1000
 set input_delay 0.46
 set output_delay 0.11
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
diff --git a/flow/designs/asap7/ethmac/config.mk b/flow/designs/asap7/ethmac/config.mk
@@ -6,7 +6,7 @@ export VERILOG_FILES         = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NIC
 export SDC_FILE              = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 40
+export CORE_UTILIZATION       = 60
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 2
-export PLACE_DENSITY          = 0.60
+export PLACE_DENSITY          = 0.75
diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name core_clock
 set clk_port_name clk_i
-set clk_period 1260
+set clk_period 1000
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/ibex/rules-base.json b/flow/designs/asap7/ibex/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -75.22,
+        "value": -212.68,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -11.43,
+        "value": -30.27,
         "compare": ">="
     }
 }
diff --git a/flow/designs/asap7/jpeg/config.mk b/flow/designs/asap7/jpeg/config.mk
@@ -8,10 +8,10 @@ export VERILOG_INCLUDE_DIRS   = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 30
+export CORE_UTILIZATION       = 70
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 2
-export PLACE_DENSITY          = 0.60
+export PLACE_DENSITY          = 0.75
 
 export TNS_END_PERCENT        = 100
 export EQUIVALENCE_CHECK     ?=   1
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 900
+set clk_period 680
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 1100
+set clk_period 600
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc
@@ -1,6 +1,6 @@
 set clk_name clock
 set clk_port_name clock
-set clk_period 100
+set clk_period 300
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc
@@ -2,7 +2,7 @@ current_design riscv_top
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 1260
+set clk_period 1000
 set clk_io_pct 0.125
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc
@@ -2,7 +2,7 @@ current_design swerv_wrapper
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 2500
+set clk_period 1600
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json
@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1867701,
+        "value": 1692500,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -359.45,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 56945,
+        "value": 56888,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
         "value": 7294,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 286,
+        "value": 1245,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -24.59,
         "compare": ">="
     }
 }
diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 300
+set clk_period 270
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/asap7/uart/rules-base.json b/flow/designs/asap7/uart/rules-base.json
@@ -48,15 +48,15 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -20.24,
+        "value": -42.58,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 103,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 36,
+        "value": 79,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc
@@ -2,7 +2,7 @@ current_design aes_cipher_top
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 3.1
+set clk_period 2.8
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc
@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 2.2
+set clk_period 1.9
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name core_clock
 set clk_port_name clk_i
-set clk_period 9.0
+set clk_period 7.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/ibex/rules-base.json b/flow/designs/sky130hs/ibex/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.19,
+        "value": -0.56,
         "compare": ">="
     },
     "finish__design__instance__area": {
diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name clk
 set clk_port_name clk
-set clk_period 6.0
+set clk_period 4.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json
@@ -28,7 +28,7 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 87,
+        "value": 336,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name clk
 set clk_port_name clk
-set clk_period 5.2
+set clk_period 4.8
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/riscv32i/rules-base.json b/flow/designs/sky130hs/riscv32i/rules-base.json
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.21,
+        "value": -0.48,
         "compare": ">="
     },
     "finish__design__instance__area": {
