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Merge pull request The-OpenROAD-Project#3428 from Pinata-Consulting/variables-openroad-hierarchical
variables: add OPENROAD_HIERARCHICAL
2 parents bbf9569 + 5ab21b6 commit 82a5c44

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-17
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-17
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docs/user/FlowVariables.md

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@@ -168,6 +168,7 @@ configuration file.
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| <a name="MAX_ROUTING_LAYER"></a>MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| |
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| <a name="MIN_BUF_CELL_AND_PORTS"></a>MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| |
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| <a name="MIN_ROUTING_LAYER"></a>MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| |
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| <a name="OPENROAD_HIERARCHICAL"></a>OPENROAD_HIERARCHICAL| Feature toggle to enable to run OpenROAD in hierarchical mode, otherwise considered flat. Will eventually be the default and this option will be retired.| 0|
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| <a name="PDN_TCL"></a>PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| |
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| <a name="PLACE_DENSITY"></a>PLACE_DENSITY| The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread. The intended effort is also communicated by this parameter. Use a low value for faster builds and higher value for better quality of results. If a too low value is used, the placer will not be able to place all cells and a recommended minimum placement density can be found in the logs. A too high value can lead to excessive runtimes, even timeouts and subtle failures in the flow after placement, such as in CTS or global routing when timing repair fails. The default is platform specific.| |
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| <a name="PLACE_DENSITY_LB_ADDON"></a>PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| |
@@ -483,6 +484,7 @@ configuration file.
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- [KLAYOUT_TECH_FILE](#KLAYOUT_TECH_FILE)
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- [LIB_FILES](#LIB_FILES)
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- [MACRO_EXTENSION](#MACRO_EXTENSION)
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- [OPENROAD_HIERARCHICAL](#OPENROAD_HIERARCHICAL)
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- [PLATFORM](#PLATFORM)
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- [PLATFORM_TCL](#PLATFORM_TCL)
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- [PROCESS](#PROCESS)

flow/scripts/load.tcl

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@@ -18,23 +18,9 @@ proc load_design { design_file sdc_file } {
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}
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}
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read_verilog $::env(RESULTS_DIR)/$design_file
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if {
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[env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
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[env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
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} {
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link_design -hier $::env(DESIGN_NAME)
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} else {
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link_design $::env(DESIGN_NAME)
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}
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log_cmd link_design {*}[hier_options] $::env(DESIGN_NAME)
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} elseif { $ext == ".odb" } {
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if {
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[env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
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[env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
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} {
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read_db -hier $::env(RESULTS_DIR)/$design_file
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} else {
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read_db $::env(RESULTS_DIR)/$design_file
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}
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log_cmd read_db {*}[hier_options] $::env(RESULTS_DIR)/$design_file
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} else {
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error "Unrecognized input file $design_file"
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}

flow/scripts/open.tcl

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@@ -16,7 +16,7 @@ if { [env_var_exists_and_non_empty DEF_FILE] } {
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log_cmd read_def $input_file
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} else {
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set input_file $::env(ODB_FILE)
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log_cmd read_db $input_file
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log_cmd read_db {*}[hier_options] $input_file
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}
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proc read_timing { input_file } {

flow/scripts/util.tcl

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@@ -186,3 +186,17 @@ proc source_env_var_if_exists { env_var } {
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log_cmd source $::env($env_var)
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}
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}
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# Feature toggle for now, eventually the -hier option
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# will be default and this code will be deleted.
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proc hier_options { } {
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if {
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[env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
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[env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] ||
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[env_var_equals OPENROAD_HIERARCHICAL 1]
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} {
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return "-hier"
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} else {
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return ""
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}
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}

flow/scripts/variables.yaml

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@@ -1039,3 +1039,9 @@ MAX_REPAIR_ANTENNAS_ITER_GRT:
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antennas will run.
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stages:
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- grt
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OPENROAD_HIERARCHICAL:
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description: >
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Feature toggle to enable to run OpenROAD in hierarchical mode,
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otherwise considered flat. Will eventually be the default and
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this option will be retired.
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default: 0

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