Merge pull request The-OpenROAD-Project#3450 from The-OpenROAD-Project-staging/tighten-rapidus-designs

tightened up rapidus designs

Author: maliberty

flow/designs/rapidus2hp/cva6/constraint.sdc

@@ -3,7 +3,7 @@
 set clk_name main_clk
 set clk_port clk_i
 set clk_ports_list [list $clk_port]
-set clk_period 1380
+set clk_period 1200
 set input_delay 0.46
 set output_delay 0.11
 create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

flow/designs/rapidus2hp/cva6/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -188.55,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -44,7 +44,7 @@
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 772,
+        "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {

flow/designs/rapidus2hp/ethmac/constraint.sdc

@@ -22,7 +22,7 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
 
 set rx_clk_name mrx_clk_pad_i
 set rx_clk_port [get_ports $rx_clk_name]
-set rx_clk_period 200
+set rx_clk_period 110
 create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
 set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
   $rx_clk_port]

flow/designs/rapidus2hp/ethmac/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -77.13,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -51.34,
         "compare": ">="
     }
 }

flow/designs/rapidus2hp/gcd/constraint.sdc

@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name core_clock
 set clk_port_name clk
-set clk_period 150
+set clk_period 100
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/rapidus2hp/gcd/rules-base.json

@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 619,
+        "value": 758,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -32,23 +32,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -8.71,
+        "value": -38.69,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 31,
+        "value": 40,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 27,
+        "value": 47,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -45.56,
         "compare": ">="
     }
 }

flow/designs/rapidus2hp/hercules_idecode/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -484.79,
+        "value": -473.42,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -75.41,
+        "value": -76.58,
         "compare": ">="
     }
 }

flow/designs/rapidus2hp/hercules_is_int/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -738.26,
+        "value": -802.81,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -80.94,
+        "value": -86.33,
         "compare": ">="
     }
 }

flow/designs/rapidus2hp/ibex/constraint.sdc

@@ -1,6 +1,6 @@
 set clk_name core_clock
 set clk_port_name clk_i
-set clk_period 790
+set clk_period 590
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/rapidus2hp/ibex/rules-base.json

@@ -32,23 +32,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -66.38,
+        "value": -116.21,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 1105,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 854,
+        "value": 1341,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -23.87,
         "compare": ">="
     }
 }