Skip to content

Commit a53c2e0

Browse files
malibertymaliberty
authored
Merge pull request The-OpenROAD-Project#3562 from dnltz/WIP/dnltz/bump-sg13g2-pdk
ihp-sg13g2: Sync PDK
2 parents 2e2d1d6 + af45b0d commit a53c2e0

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

44 files changed

+136684
-104196
lines changed

‎flow/designs/ihp-sg13g2/aes/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,4 +140,4 @@
140140
"value": 1054989,
141141
"compare": "<="
142142
}
143-
}
143+
}

‎flow/designs/ihp-sg13g2/gcd/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design gcd
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 2.6
5+
set clk_period 2.8
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/ihp-sg13g2/gcd/rules-base.json‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,19 +30,19 @@
3030
"level": "warning"
3131
},
3232
"synth__design__instance__area__stdcell": {
33-
"value": 5458.22361,
33+
"value": 6828.9632,
3434
"compare": "<="
3535
},
3636
"constraints__clocks__count": {
3737
"value": 1,
3838
"compare": "=="
3939
},
4040
"placeopt__design__instance__area": {
41-
"value": 6195,
41+
"value": 7382,
4242
"compare": "<="
4343
},
4444
"placeopt__design__instance__count__stdcell": {
45-
"value": 494,
45+
"value": 614,
4646
"compare": "<="
4747
},
4848
"detailedplace__design__violations": {
@@ -94,7 +94,7 @@
9494
"compare": ">="
9595
},
9696
"detailedroute__route__wirelength": {
97-
"value": 12621,
97+
"value": 15132,
9898
"compare": "<="
9999
},
100100
"detailedroute__route__drc_errors": {
@@ -142,7 +142,7 @@
142142
"compare": ">="
143143
},
144144
"finish__design__instance__area": {
145-
"value": 26057,
145+
"value": 7693,
146146
"compare": "<="
147147
}
148-
}
148+
}

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/pdn.tcl‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -25,14 +25,14 @@ global_connect
2525
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
2626

2727
# stdcell grid
28-
define_pdn_grid -name {grid} -voltage_domains {CORE}
28+
define_pdn_grid -name {grid} -voltage_domains {CORE} -pins {Metal4 Metal5}
2929
add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \
30-
-followpins -extend_to_core_ring
31-
add_pdn_ring -grid {grid} -layers {Metal3 Metal4} -widths {3.0} -spacings {2.0} \
30+
-followpins
31+
add_pdn_ring -grid {grid} -layers {Metal4 Metal5} -widths {3.0} -spacings {2.0} \
3232
-core_offsets {4.5} -connect_to_pads
33-
add_pdn_stripe -grid {grid} -layer {Metal3} -width {1.840} -pitch {75.6} -offset {37.8} \
33+
add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {13.6} \
3434
-extend_to_core_ring
35-
add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.840} -pitch {75.6} -offset {37.8} \
35+
add_pdn_stripe -grid {grid} -layer {Metal5} -width {1.840} -pitch {75.6} -offset {13.6} \
3636
-extend_to_core_ring
37-
add_pdn_connect -grid {grid} -layers {Metal1 Metal3}
38-
add_pdn_connect -grid {grid} -layers {Metal3 Metal4}
37+
add_pdn_connect -grid {grid} -layers {Metal1 Metal4}
38+
add_pdn_connect -grid {grid} -layers {Metal4 Metal5}

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,14 +8,14 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz
1010

11-
export DIE_AREA = 0.0 0.0 1050.0 1050.0
11+
export DIE_AREA = 0.0 0.0 1050.24 1050.84
1212
export CORE_AREA = 351.36 351.54 699.84 699.3
1313

1414
export MAX_ROUTING_LAYER = TopMetal2
1515

1616
export TNS_END_PERCENT = 100
1717
export PLACE_DENSITY = 0.75
18-
18+
export MACRO_PLACE_HALO = 20 20
1919
export CORNERS = slow fast
2020

2121
export FOOTPRINT_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/pad.tcl

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/constraint.sdc‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@ create_clock [get_pins sg13g2_IOPad_io_clock/p2c] -name clk_core -period 20.0 -w
1010
set_clock_uncertainty 0.15 [get_clocks clk_core]
1111
set_clock_transition 0.25 [get_clocks clk_core]
1212

13+
set input_delay_value_clk_core 4.0
14+
set output_delay_value_clk_core 4.0
15+
1316
set clock_ports [get_ports {
1417
io_clock_PAD
1518
}]
@@ -26,16 +29,16 @@ set clk_core_inout_16mA_ports [get_ports {
2629
io_gpio_7_PAD
2730
}]
2831
set_driving_cell -lib_cell sg13g2_IOPadInOut16mA -pin pad $clk_core_inout_16mA_ports
29-
set_input_delay 8 -clock clk_core $clk_core_inout_16mA_ports
30-
set_output_delay 8 -clock clk_core $clk_core_inout_16mA_ports
32+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
33+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_16mA_ports
3134

3235
set clk_core_inout_4mA_ports [get_ports {
3336
io_i2c_scl_PAD
3437
io_i2c_sda_PAD
3538
}]
3639
set_driving_cell -lib_cell sg13g2_IOPadInOut4mA -pin pad $clk_core_inout_4mA_ports
37-
set_input_delay 8 -clock clk_core $clk_core_inout_4mA_ports
38-
set_output_delay 8 -clock clk_core $clk_core_inout_4mA_ports
40+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
41+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_inout_4mA_ports
3942

4043
set clk_core_input_ports [get_ports {
4144
io_reset_PAD
@@ -44,13 +47,13 @@ set clk_core_input_ports [get_ports {
4447
io_address_2_PAD
4548
}]
4649
set_driving_cell -lib_cell sg13g2_IOPadIn -pin pad $clk_core_input_ports
47-
set_input_delay 8 -clock clk_core $clk_core_input_ports
50+
set_input_delay $input_delay_value_clk_core -clock clk_core $clk_core_input_ports
4851

4952
set clk_core_output_4mA_ports [get_ports {
5053
io_i2c_interrupt_PAD
5154
}]
5255
set_driving_cell -lib_cell sg13g2_IOPadOut4mA -pin pad $clk_core_output_4mA_ports
53-
set_output_delay 8 -clock clk_core $clk_core_output_4mA_ports
56+
set_output_delay $output_delay_value_clk_core -clock clk_core $clk_core_output_4mA_ports
5457

5558
set_load -pin_load 5 [all_inputs]
5659
set_load -pin_load 5 [all_outputs]

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,22 +25,20 @@ global_connect
2525
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
2626

2727
# stdcell grid
28-
define_pdn_grid -name {grid} -voltage_domains {CORE}
28+
define_pdn_grid -name {grid} -voltage_domains {CORE} -pins {TopMetal1 TopMetal2}
2929
add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} \
3030
-followpins -extend_to_core_ring
31-
add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {8.0} -spacings {5.0} \
31+
add_pdn_ring -grid {grid} -layers {TopMetal1 TopMetal2} -widths {8.0} -spacings {5.0} \
3232
-core_offsets {4.5} -connect_to_pads
33-
add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {37.8} \
33+
add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {13.6} \
3434
-extend_to_core_ring
35-
add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {2.200} -pitch {75.6} -offset {37.8} \
35+
add_pdn_stripe -grid {grid} -layer {TopMetal2} -width {2.200} -pitch {75.6} -offset {13.6} \
3636
-extend_to_core_ring
37-
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
38-
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
39-
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2}
37+
add_pdn_connect -grid {grid} -layers {Metal1 TopMetal1}
4038
add_pdn_connect -grid {grid} -layers {TopMetal1 TopMetal2}
4139

4240
define_pdn_grid \
4341
-name {CORE_macro_grid_1} -voltage_domains {CORE} \
4442
-macro -cells {I2cDeviceCtrl} -grid_over_boundary
45-
add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal3 TopMetal1}
4643
add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal4 TopMetal1}
44+
add_pdn_connect -grid {CORE_macro_grid_1} -layers {Metal5 TopMetal1}

‎flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,19 +97,19 @@
9797
"compare": "<="
9898
},
9999
"placeopt__design__instance__count__stdcell": {
100-
"value": 965,
100+
"value": 953,
101101
"compare": "<="
102102
},
103103
"detailedplace__design__violations": {
104104
"value": 0,
105105
"compare": "=="
106106
},
107107
"cts__design__instance__count__setup_buffer": {
108-
"value": 84,
108+
"value": 83,
109109
"compare": "<="
110110
},
111111
"cts__design__instance__count__hold_buffer": {
112-
"value": 84,
112+
"value": 83,
113113
"compare": "<="
114114
},
115115
"cts__timing__setup__ws": {
@@ -197,7 +197,7 @@
197197
"compare": ">="
198198
},
199199
"finish__design__instance__area": {
200-
"value": 135675,
200+
"value": 42034,
201201
"compare": "<="
202202
}
203203
}

‎flow/designs/ihp-sg13g2/ibex/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
1515
# Adders degrade ibex setup repair
1616
export ADDER_MAP_FILE :=
1717

18-
export CORE_UTILIZATION = 45
18+
export CORE_UTILIZATION = 35
1919
export PLACE_DENSITY_LB_ADDON = 0.2
2020
export TNS_END_PERCENT = 100
21-
export CTS_BUF_DISTANCE = 60
21+
export CTS_BUF_DISTANCE = 60

‎flow/designs/ihp-sg13g2/ibex/rules-base.json‎

Lines changed: 2 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,4 @@
11
{
2-
"detailedroute__flow__warnings__count:DRT-0349": {
3-
"value": 10,
4-
"compare": "<=",
5-
"level": "warning"
6-
},
7-
"finish__flow__warnings__count:GUI-0076": {
8-
"value": 1,
9-
"compare": "<=",
10-
"level": "warning"
11-
},
12-
"floorplan__flow__warnings__count:EST-0027": {
13-
"value": 1,
14-
"compare": "<=",
15-
"level": "warning"
16-
},
17-
"floorplan__flow__warnings__count:IFP-0028": {
18-
"value": 1,
19-
"compare": "<=",
20-
"level": "warning"
21-
},
22-
"globalroute__flow__warnings__count:DRT-0349": {
23-
"value": 10,
24-
"compare": "<=",
25-
"level": "warning"
26-
},
272
"synth__design__instance__area__stdcell": {
283
"value": 305820.24,
294
"compare": "<="
@@ -89,7 +64,7 @@
8964
"compare": ">="
9065
},
9166
"detailedroute__route__wirelength": {
92-
"value": 999955,
67+
"value": 989089,
9368
"compare": "<="
9469
},
9570
"detailedroute__route__drc_errors": {
@@ -137,7 +112,7 @@
137112
"compare": ">="
138113
},
139114
"finish__design__instance__area": {
140-
"value": 645302,
115+
"value": 314511,
141116
"compare": "<="
142117
}
143118
}

0 commit comments

Comments
 (0)