Merge pull request The-OpenROAD-Project#3434 from The-OpenROAD-Project-staging/secure-opto-flow

Added flow support for new optimization transformns

Author: maliberty

docs/user/FlowVariables.md

@@ -222,7 +222,9 @@ configuration file.
 | <a name="SKIP_INCREMENTAL_REPAIR"></a>SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0|
 | <a name="SKIP_LAST_GASP"></a>SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| |
 | <a name="SKIP_PIN_SWAP"></a>SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| |
+| <a name="SKIP_REPAIR_TIE_FANOUT"></a>SKIP_REPAIR_TIE_FANOUT| Skip repair_tie_fanout at floorplan step.| |
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| |
+| <a name="SKIP_VT_SWAP"></a>SKIP_VT_SWAP| Do not perform VT swap to improve QoR (default: do VT swap).| |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
 | <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
@@ -236,6 +238,7 @@ configuration file.
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096|
 | <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0|
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
+| <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| |
 | <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| List of modules to apply retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. This is an experimental option and may cause adverse effects.| |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
@@ -273,6 +276,7 @@ configuration file.
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
 - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE)
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
+- [SYNTH_OPT_HIER](#SYNTH_OPT_HIER)
 - [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
@@ -332,7 +336,9 @@ configuration file.
 - [SKIP_GATE_CLONING](#SKIP_GATE_CLONING)
 - [SKIP_LAST_GASP](#SKIP_LAST_GASP)
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
+- [SKIP_REPAIR_TIE_FANOUT](#SKIP_REPAIR_TIE_FANOUT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SKIP_VT_SWAP](#SKIP_VT_SWAP)
 - [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TAPCELL_TCL](#TAPCELL_TCL)
@@ -387,6 +393,7 @@ configuration file.
 - [SKIP_LAST_GASP](#SKIP_LAST_GASP)
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SKIP_VT_SWAP](#SKIP_VT_SWAP)
 - [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
@@ -410,6 +417,7 @@ configuration file.
 - [SKIP_LAST_GASP](#SKIP_LAST_GASP)
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SKIP_VT_SWAP](#SKIP_VT_SWAP)
 - [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)

flow/scripts/floorplan.tcl

@@ -95,21 +95,23 @@ if { [env_var_exists_and_non_empty MAKE_TRACKS] } {
 
 source_env_var_if_exists FOOTPRINT_TCL
 
-# This needs to come before any call to remove_buffers.  You could have one
-# tie driving multiple buffers that drive multiple outputs.
-# Repair tie lo fanout
-puts "Repair tie lo fanout..."
-set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
-set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
-
-# Repair tie hi fanout
-puts "Repair tie hi fanout..."
-set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
-set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
+if { ![env_var_equal SKIP_REPAIR_TIE_FANOUT 1] } {
+  # This needs to come before any call to remove_buffers.  You could have one
+  # tie driving multiple buffers that drive multiple outputs.
+  # Repair tie lo fanout
+  puts "Repair tie lo fanout..."
+  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
+
+  # Repair tie hi fanout
+  puts "Repair tie hi fanout..."
+  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
+}
 
 if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
   estimate_parasitics -placement
@@ -121,7 +123,7 @@ if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   remove_buffers
 } else {
   # Skip clone & split
-  set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer"
+  set ::env(SETUP_MOVE_SEQUENCE) "unbuffer,sizeup,swap,buffer,vt_swap"
   set ::env(SKIP_LAST_GASP) 1
   repair_timing_helper -setup
 }

flow/scripts/synth.tcl

@@ -28,6 +28,9 @@ if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
   set synth_full_args [concat $synth_full_args \
     "-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
 }
+if { [env_var_exists_and_non_empty SYNTH_OPT_HIER] } {
+  set synth_full_args [concat $synth_full_args -hieropt]
+}
 
 if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
   # Perform standard coarse-level synthesis script, flatten right away
@@ -39,7 +42,8 @@ if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
 
   if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } {
     set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE)
-    puts "Keep modules above estimated size of $ungroup_threshold gate equivalents"
+    puts "Keep modules above estimated size of " \
+      "$ungroup_threshold gate equivalents"
 
     convert_liberty_areas
     keep_hierarchy -min_cost $ungroup_threshold
@@ -130,7 +134,8 @@ if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
   delete {t:$specify*}
 }
 
-# Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..})
+# Splitting nets resolves unwanted compound assign statements in
+# netlist (assign {..} = {..})
 splitnets
 
 # Remove unused cells and wires
@@ -149,7 +154,8 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
 
 tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
 
-# check the design is composed exclusively of target cells, and check for other problems
+# check the design is composed exclusively of target cells, and
+# check for other problems
 if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
   check -assert -mapped
 } else {

flow/scripts/util.tcl

@@ -25,6 +25,7 @@ proc repair_timing_helper { args } {
   append_env_var additional_args SKIP_GATE_CLONING -skip_gate_cloning 0
   append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
   append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
+  append_env_var additional_args SKIP_VT_SWAP -skip_vt_swap 0
   append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   log_cmd repair_timing {*}$additional_args
 }

flow/scripts/variables.yaml

@@ -573,6 +573,13 @@ SKIP_PIN_SWAP:
     - cts
     - floorplan
     - grt
+SKIP_VT_SWAP:
+  description: >
+    Do not perform VT swap to improve QoR (default: do VT swap).
+  stages:
+    - cts
+    - floorplan
+    - grt
 REMOVE_CELLS_FOR_EQY:
   description: >
     String patterns directly passed to write_verilog -remove_cells <> for
@@ -585,6 +592,11 @@ SKIP_CTS_REPAIR_TIMING:
     architectural exploration or when getting CI up and running.
   stages:
     - cts
+SKIP_REPAIR_TIE_FANOUT:
+  description: >
+    Skip repair_tie_fanout at floorplan step.
+  stages:
+    - floorplan
 MIN_ROUTING_LAYER:
   description: |
     The lowest metal layer name to be used in routing.
@@ -732,6 +744,11 @@ SYNTH_HIER_SEPARATOR:
   description: |
     Separator used for the synthesis flatten stage.
   default: .
+SYNTH_OPT_HIER:
+  description: |
+    Optimize constants across hierarchical boundaries.
+  stages:
+    - synth
 VERILOG_TOP_PARAMS:
   description: |
     Apply toplevel params (if exist).