Merge branch 'master' into secure-yosys0.57

Signed-off-by: Eder Monteiro <[email protected]>

Author: eder-matheus

docs/user/FlowVariables.md

@@ -155,7 +155,6 @@ configuration file.
 | <a name="LIB_FILES"></a>LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
 | <a name="MACRO_BLOCKAGE_HALO"></a>MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
 | <a name="MACRO_EXTENSION"></a>MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
-| <a name="MACRO_PLACEMENT"></a>MACRO_PLACEMENT| Specifies the path of a file on how to place certain macros manually using read_macro_placement.| |
 | <a name="MACRO_PLACEMENT_TCL"></a>MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place certain macros manually.| |
 | <a name="MACRO_PLACE_HALO"></a>MACRO_PLACE_HALO| Horizontal/vertical halo around macros (microns). Used by automatic macro placement.| |
 | <a name="MACRO_ROWS_HALO_X"></a>MACRO_ROWS_HALO_X| Horizontal distance between the edge of the macro and the beginning of the rows created by tapcell. Only available for ASAP7 PDK and GF180/uart-blocks design.| |
@@ -299,7 +298,6 @@ configuration file.
 - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
 - [IO_CONSTRAINTS](#IO_CONSTRAINTS)
 - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO)
-- [MACRO_PLACEMENT](#MACRO_PLACEMENT)
 - [MACRO_PLACEMENT_TCL](#MACRO_PLACEMENT_TCL)
 - [MACRO_PLACE_HALO](#MACRO_PLACE_HALO)
 - [MACRO_ROWS_HALO_X](#MACRO_ROWS_HALO_X)

flow/designs/rapidus2hp/hercules_is_int/config.mk

@@ -25,7 +25,7 @@ export SYNTH_HIERARCHICAL    ?= 0
 ifeq ($(PLACE_SITE), SC6T)
   export CORE_UTILIZATION     = 30
 else
-  export CORE_UTILIZATION     = 35
+  export CORE_UTILIZATION     = 54
 endif
 
 export CORE_MARGIN            = 1
@@ -35,6 +35,12 @@ export PLACE_DENSITY          = 0.58
 # few last gasp iterations
 export SKIP_LAST_GASP ?= 1
 
+export PLACE_PINS_ARGS = -min_distance_in_tracks -min_distance 1
+export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 0
+export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 0
+# temporarily skip over DPO to bypass one-site gap issues
+export ENABLE_DPO = 0
+
 # Selectively keep module hierarchies to match baseline data
 # ifeq ($(SYNTH_HDL_FRONTEND), verific)
 #   export SYNTH_KEEP_MODULES = \hercules_is_grbt \

flow/designs/rapidus2hp/hercules_is_int/rules-base.json

@@ -8,47 +8,47 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 36794,
+        "value": 34339,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 750846,
+        "value": 747172,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 65291,
+        "value": 64972,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 65291,
+        "value": 64972,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -736.52,
+        "value": -435.93,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 37950,
+        "value": 35330,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 32646,
+        "value": 32486,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 284,
+        "value": 110,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -79.76,
+        "value": -66.06,
         "compare": ">="
     }
 }

flow/designs/sky130hd/chameleon/chameleon.macro_placment.cfg

@@ -44,7 +44,7 @@ export ADDITIONAL_LEFS  = $(chameleon_DIR)/lef/apb_sys_0.lef \
                           $(chameleon_DIR)/lef/DMC_32x16HC.lef \
                           $(chameleon_DIR)/lef/ibex_wrapper.lef
 
-export MACRO_PLACEMENT = $(chameleon_DIR)/chameleon.macro_placment.cfg
+export MACRO_PLACEMENT_TCL = $(chameleon_DIR)/macro_placement.tcl
 
 export FP_PDN_RAIL_WIDTH  = 0.48
 export FP_PDN_RAIL_OFFSET = 0

flow/designs/sky130hd/chameleon/config.mk

@@ -0,0 +1,6 @@
+place_macro -macro_name {RAM.genblk1\[0\].RAM} -location {200 150} -orientation R0
+place_macro -macro_name {RAM.genblk1\[1\].RAM} -location {1600 150} -orientation R0
+place_macro -macro_name {RAM.genblk1\[2\].RAM} -location {200 1950} -orientation R180
+place_macro -macro_name {ahb_sys_0_uut.S0.CACHE} -location {2100 2650} -orientation R0
+place_macro -macro_name {ahb_sys_0_uut.apb_sys_inst_0} -location {1470 2643} -orientation R0
+place_macro -macro_name {ibex_core} -location {2150 1700} -orientation R0

flow/designs/sky130hd/chameleon/macro_placement.tcl

@@ -36,9 +36,6 @@ if { [find_macros] != "" } {
 
   if { [env_var_exists_and_non_empty MACRO_PLACEMENT_TCL] } {
     log_cmd source $::env(MACRO_PLACEMENT_TCL)
-  } elseif { [env_var_exists_and_non_empty MACRO_PLACEMENT] } {
-    source $::env(SCRIPTS_DIR)/read_macro_placement.tcl
-    log_cmd read_macro_placement $::env(MACRO_PLACEMENT)
   } else {
     set additional_rtlmp_args ""
     append_env_var additional_rtlmp_args RTLMP_MAX_LEVEL -max_num_level 1

flow/scripts/macro_place_util.tcl

@@ -341,12 +341,6 @@ TAPCELL_TCL:
     Path to Endcap and Welltie cells file.
   stages:
     - floorplan
-MACRO_PLACEMENT:
-  description: >
-    Specifies the path of a file on how to place certain macros manually using
-    read_macro_placement.
-  stages:
-    - floorplan
 MACRO_PLACEMENT_TCL:
   description: |
     Specifies the path of a TCL file on how to place certain macros manually.

flow/scripts/read_macro_placement.tcl

@@ -17,7 +17,7 @@ ISSUE_CP_DESIGN_FILE_VARS="SDC_FILE \
                            FOOTPRINT \
                            SIG_MAP_FILE \
                            IO_CONSTRAINTS \
-                           MACRO_PLACEMENT \
+                           MACRO_PLACEMENT_TCL \
                            MACRO_WRAPPERS \
                            RTLMP_CONFIG_FILE \
                            DFF_LIB_FILE "