Skip to content

Commit f19db0e

Browse files
precisionmoonprecisionmoon
committed
yet another tclint fix
Signed-off-by: Cho Moon <[email protected]>
1 parent 20c7b84 commit f19db0e

File tree

1 file changed

+85
-82
lines changed

1 file changed

+85
-82
lines changed

‎flow/scripts/synth.tcl‎

Lines changed: 85 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -3,79 +3,80 @@ read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
33

44
hierarchy -check -top $::env(DESIGN_NAME)
55

6-
if {[env_var_equals SYNTH_GUT 1]} {
7-
# /deletes all cells at the top level, which will quickly optimize away
8-
# everything else, including macros.
9-
delete $::env(DESIGN_NAME)/c:*
6+
if { [env_var_equals SYNTH_GUT 1] } {
7+
# /deletes all cells at the top level, which will quickly optimize away
8+
# everything else, including macros.
9+
delete $::env(DESIGN_NAME)/c:*
1010
}
1111

12-
if {[env_var_exists_and_non_empty SYNTH_KEEP_MODULES]} {
13-
foreach module $::env(SYNTH_KEEP_MODULES) {
14-
select -module $module
15-
setattr -mod -set keep_hierarchy 1
16-
select -clear
17-
}
12+
if { [env_var_exists_and_non_empty SYNTH_KEEP_MODULES] } {
13+
foreach module $::env(SYNTH_KEEP_MODULES) {
14+
select -module $module
15+
setattr -mod -set keep_hierarchy 1
16+
select -clear
17+
}
1818
}
1919

20-
if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} {
21-
scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
20+
if { [env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR] } {
21+
scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
2222
}
2323

2424
set synth_full_args [env_var_or_empty SYNTH_ARGS]
25-
if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
26-
set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
25+
if { [env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS] } {
26+
set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
2727
} else {
28-
set synth_full_args [concat $synth_full_args \
29-
"-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
28+
set synth_full_args [concat $synth_full_args \
29+
"-extra-map $::env(FLOW_HOME)/platforms/common/lcu_kogge_stone.v"]
3030
}
31-
if {[env_var_exists_and_non_empty SYNTH_OPT_HIER]} {
32-
set synth_full_args [concat $synth_full_args -hieropt]
31+
if { [env_var_exists_and_non_empty SYNTH_OPT_HIER] } {
32+
set synth_full_args [concat $synth_full_args -hieropt]
3333
}
3434

35-
if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
36-
# Perform standard coarse-level synthesis script, flatten right away
37-
synth -flatten -run :fine {*}$synth_full_args
35+
if { ![env_var_equals SYNTH_HIERARCHICAL 1] } {
36+
# Perform standard coarse-level synthesis script, flatten right away
37+
synth -flatten -run :fine {*}$synth_full_args
3838
} else {
39-
# Perform standard coarse-level synthesis script,
40-
# defer flattening until we have decided what hierarchy to keep
41-
synth -run :fine
42-
43-
if {[env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE]} {
44-
set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE)
45-
puts "Keep modules above estimated size of $ungroup_threshold gate equivalents"
46-
47-
convert_liberty_areas
48-
keep_hierarchy -min_cost $ungroup_threshold
49-
} else {
50-
keep_hierarchy
51-
}
52-
53-
# Re-run coarse-level script, this time do pass -flatten
54-
synth -flatten -run coarse:fine {*}$synth_full_args
39+
# Perform standard coarse-level synthesis script,
40+
# defer flattening until we have decided what hierarchy to keep
41+
synth -run :fine
42+
43+
if { [env_var_exists_and_non_empty SYNTH_MINIMUM_KEEP_SIZE] } {
44+
set ungroup_threshold $::env(SYNTH_MINIMUM_KEEP_SIZE)
45+
puts "Keep modules above estimated size of " \
46+
"$ungroup_threshold gate equivalents"
47+
48+
convert_liberty_areas
49+
keep_hierarchy -min_cost $ungroup_threshold
50+
} else {
51+
keep_hierarchy
52+
}
53+
54+
# Re-run coarse-level script, this time do pass -flatten
55+
synth -flatten -run coarse:fine {*}$synth_full_args
5556
}
5657

5758
json -o $::env(RESULTS_DIR)/mem.json
5859
# Run report and check here so as to fail early if this synthesis run is doomed
5960
exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \
60-
--max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
61-
62-
if {[env_var_exists_and_non_empty SYNTH_RETIME_MODULES]} {
63-
select $::env(SYNTH_RETIME_MODULES)
64-
opt -fast -full
65-
memory_map
66-
opt -full
67-
techmap
68-
abc -dff -script $::env(SCRIPTS_DIR)/abc_retime.script
69-
select -clear
61+
--max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
62+
63+
if { [env_var_exists_and_non_empty SYNTH_RETIME_MODULES] } {
64+
select $::env(SYNTH_RETIME_MODULES)
65+
opt -fast -full
66+
memory_map
67+
opt -full
68+
techmap
69+
abc -dff -script $::env(SCRIPTS_DIR)/abc_retime.script
70+
select -clear
7071
}
7172

7273
if {
73-
[env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
74-
[env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
74+
[env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
75+
[env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
7576
} {
76-
source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
77+
source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
7778
} else {
78-
synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args
79+
synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args
7980
}
8081

8182
# Get rid of indigestibles
@@ -91,58 +92,59 @@ renames -wire
9192
opt -purge
9293

9394
# Technology mapping of adders
94-
if {[env_var_exists_and_non_empty ADDER_MAP_FILE]} {
95-
# extract the full adders
96-
extract_fa
97-
# map full adders
98-
techmap -map $::env(ADDER_MAP_FILE)
99-
techmap
100-
# Quick optimization
101-
opt -fast -purge
95+
if { [env_var_exists_and_non_empty ADDER_MAP_FILE] } {
96+
# extract the full adders
97+
extract_fa
98+
# map full adders
99+
techmap -map $::env(ADDER_MAP_FILE)
100+
techmap
101+
# Quick optimization
102+
opt -fast -purge
102103
}
103104

104105
# Technology mapping of latches
105-
if {[env_var_exists_and_non_empty LATCH_MAP_FILE]} {
106-
techmap -map $::env(LATCH_MAP_FILE)
106+
if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
107+
techmap -map $::env(LATCH_MAP_FILE)
107108
}
108109

109110
set dfflibmap_args ""
110111
foreach cell $::env(DONT_USE_CELLS) {
111-
lappend dfflibmap_args -dont_use $cell
112+
lappend dfflibmap_args -dont_use $cell
112113
}
113114

114115
# Technology mapping of flip-flops
115116
# dfflibmap only supports one liberty file
116-
if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
117-
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
117+
if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
118+
dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
118119
} else {
119-
dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
120+
dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
120121
}
121122
opt
122123

123124
# Replace undef values with defined constants
124125
setundef -zero
125126

126-
if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
127-
log_cmd abc {*}$abc_args
127+
if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
128+
log_cmd abc {*}$abc_args
128129
} else {
129-
scratchpad -set abc9.script $::env(SCRIPTS_DIR)/abc_speed_gia_only.script
130-
# crop out -script from arguments
131-
set abc_args [lrange $abc_args 2 end]
132-
log_cmd abc_new {*}$abc_args
133-
delete {t:$specify*}
130+
scratchpad -set abc9.script $::env(SCRIPTS_DIR)/abc_speed_gia_only.script
131+
# crop out -script from arguments
132+
set abc_args [lrange $abc_args 2 end]
133+
log_cmd abc_new {*}$abc_args
134+
delete {t:$specify*}
134135
}
135136

136-
# Splitting nets resolves unwanted compound assign statements in netlist (assign {..} = {..})
137+
# Splitting nets resolves unwanted compound assign statements in
138+
# netlist (assign {..} = {..})
137139
splitnets
138140

139141
# Remove unused cells and wires
140142
opt_clean -purge
141143

142144
# Technology mapping of constant hi- and/or lo-drivers
143145
hilomap -singleton \
144-
-hicell {*}$::env(TIEHI_CELL_AND_PORT) \
145-
-locell {*}$::env(TIELO_CELL_AND_PORT)
146+
-hicell {*}$::env(TIEHI_CELL_AND_PORT) \
147+
-locell {*}$::env(TIELO_CELL_AND_PORT)
146148

147149
# Insert buffer cells for pass through wires
148150
insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)
@@ -152,14 +154,15 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
152154

153155
tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
154156

155-
# check the design is composed exclusively of target cells, and check for other problems
156-
if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
157-
check -assert -mapped
157+
# check the design is composed exclusively of target cells, and
158+
# check for other problems
159+
if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
160+
check -assert -mapped
158161
} else {
159-
# Wrapped operator synthesis leaves around $buf cells which `check -mapped`
160-
# gets confused by, once Yosys#4931 is merged we can remove this branch and
161-
# always run `check -assert -mapped`
162-
check -assert
162+
# Wrapped operator synthesis leaves around $buf cells which `check -mapped`
163+
# gets confused by, once Yosys#4931 is merged we can remove this branch and
164+
# always run `check -assert -mapped`
165+
check -assert
163166
}
164167

165168
# Write synthesized design

0 commit comments

Comments
 (0)