Skip to content

Commit 704d2f2

Browse files
dpgeorgedpgeorge
committed
alif/boards/OPENMV_AE3: Add OpenMV AE3 board definition.
Supports Murata 1YN for WiFi and BLE. Signed-off-by: iabdalkader <[email protected]> Signed-off-by: Damien George <[email protected]>
1 parent 7c216d1 commit 704d2f2

File tree

6 files changed

+388
-0
lines changed

6 files changed

+388
-0
lines changed

‎ports/alif/boards/OPENMV_AE3/board.c‎

Lines changed: 192 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,192 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2024 OpenMV LLC.
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "py/mphal.h"
28+
#include "ospi_ext.h"
29+
#include "ospi_flash.h"
30+
#include "se_services.h"
31+
32+
#define OMV_BOOT_MAGIC_ADDR (0x200FFFFCU)
33+
#define OMV_BOOT_MAGIC_VALUE (0xB00710ADU)
34+
35+
#if CORE_M55_HP
36+
#define NPU_IRQ_NUMBER NPU_HP_IRQ_IRQn
37+
#define NPU_BASE_ADDRESS (void *)NPU_HP_BASE
38+
#else
39+
#define NPU_IRQ_NUMBER NPU_HE_IRQ_IRQn
40+
#define NPU_BASE_ADDRESS (void *)NPU_HE_BASE
41+
#endif
42+
43+
typedef struct {
44+
volatile uint32_t ID; // 0x0
45+
volatile uint32_t STATUS; // 0x4
46+
volatile uint32_t CMD; // 0x8
47+
volatile uint32_t RESET; // 0xC
48+
} npu_regs_t;
49+
50+
#define NPU ((npu_regs_t *)NPU_BASE_ADDRESS)
51+
52+
const ospi_pin_settings_t ospi_pin_settings = {
53+
.peripheral_number = 0,
54+
.pin_reset = pin_FLASH_RESET,
55+
.pin_cs = pin_FLASH_CS,
56+
.pin_clk_p = pin_FLASH_SCLK_P,
57+
.pin_clk_n = pin_FLASH_SCLK_N,
58+
.pin_rwds = pin_FLASH_DQSM,
59+
.pin_d0 = pin_FLASH_D0,
60+
.pin_d1 = pin_FLASH_D1,
61+
.pin_d2 = pin_FLASH_D2,
62+
.pin_d3 = pin_FLASH_D3,
63+
.pin_d4 = pin_FLASH_D4,
64+
.pin_d5 = pin_FLASH_D5,
65+
.pin_d6 = pin_FLASH_D6,
66+
.pin_d7 = pin_FLASH_D7,
67+
};
68+
69+
const ospi_flash_settings_t ospi_flash_settings[] = {
70+
{
71+
.jedec_id = 0x3980c2,
72+
.freq_hz = 100000000,
73+
.read_dummy_cycles = 10,
74+
OSPI_FLASH_SETTINGS_MX25,
75+
},
76+
{
77+
.jedec_id = 0x195b9d,
78+
.freq_hz = 100000000,
79+
.read_dummy_cycles = 9,
80+
OSPI_FLASH_SETTINGS_IS25,
81+
},
82+
{
83+
.jedec_id = 0x17bb6b,
84+
.freq_hz = 100000000,
85+
.read_dummy_cycles = 7,
86+
OSPI_FLASH_SETTINGS_EM,
87+
},
88+
};
89+
const size_t ospi_flash_settings_len = 3;
90+
91+
void board_startup(void) {
92+
// Switch the USB multiplexer to use the Alif USB port.
93+
mp_hal_pin_output(pin_USB_D_SEL);
94+
mp_hal_pin_high(pin_USB_D_SEL);
95+
}
96+
97+
void board_enter_bootloader(void) {
98+
*((uint32_t *)OMV_BOOT_MAGIC_ADDR) = OMV_BOOT_MAGIC_VALUE;
99+
NVIC_SystemReset();
100+
}
101+
102+
void board_early_init(void) {
103+
// Set default run profile
104+
run_profile_t run_profile = {
105+
.dcdc_mode = DCDC_MODE_PWM,
106+
.dcdc_voltage = DCDC_VOUT_0825,
107+
// CLK_SRC_LFRC or CLK_SRC_LFXO
108+
.aon_clk_src = CLK_SRC_LFXO,
109+
// CLK_SRC_HFRC, CLK_SRC_HFXO or CLK_SRC_PLL
110+
.run_clk_src = CLK_SRC_PLL,
111+
#if CORE_M55_HP
112+
.cpu_clk_freq = CLOCK_FREQUENCY_400MHZ,
113+
#else
114+
.cpu_clk_freq = CLOCK_FREQUENCY_160MHZ,
115+
#endif
116+
.scaled_clk_freq = SCALED_FREQ_XO_HIGH_DIV_38_4_MHZ,
117+
// AON, modem aon, SSE-700 AON, modem, SYSTOP, DEBUG, SE
118+
.power_domains = PD_VBAT_AON_MASK | PD_SSE700_AON_MASK | PD_SYST_MASK |
119+
PD_DBSS_MASK | PD_SESS_MASK | PD_SRAMS_MASK | PD_SRAM_CTRL_AON_MASK,
120+
// Add all memories
121+
.memory_blocks = SERAM_MASK | SRAM0_MASK | SRAM1_MASK | MRAM_MASK | BACKUP4K_MASK |
122+
SRAM6A_MASK | SRAM6B_MASK | SRAM7_1_MASK | SRAM7_2_MASK | SRAM7_3_MASK |
123+
SRAM8_MASK | SRAM9_MASK | FWRAM_MASK,
124+
.phy_pwr_gating = LDO_PHY_MASK | USB_PHY_MASK | MIPI_TX_DPHY_MASK | MIPI_RX_DPHY_MASK |
125+
MIPI_PLL_DPHY_MASK,
126+
.vdd_ioflex_3V3 = IOFLEX_LEVEL_3V3,
127+
};
128+
129+
if (se_services_set_run_profile(&run_profile)) {
130+
MICROPY_BOARD_FATAL_ERROR("se_services_set_run_profile");
131+
}
132+
133+
// Set default off profile
134+
off_profile_t off_profile = {
135+
.dcdc_mode = DCDC_MODE_PWM,
136+
.dcdc_voltage = DCDC_VOUT_0825,
137+
// CLK_SRC_LFRC or CLK_SRC_LFXO
138+
.aon_clk_src = CLK_SRC_LFXO,
139+
// CLK_SRC_HFRC, CLK_SRC_HFXO or CLK_SRC_PLL
140+
.stby_clk_src = CLK_SRC_HFRC,
141+
.stby_clk_freq = SCALED_FREQ_RC_STDBY_76_8_MHZ,
142+
// Disable all power domains.
143+
.power_domains = 0,
144+
// Add all memories
145+
.memory_blocks = SERAM_MASK | SRAM0_MASK | SRAM1_MASK | MRAM_MASK | BACKUP4K_MASK |
146+
SRAM6A_MASK | SRAM6B_MASK | SRAM7_1_MASK | SRAM7_2_MASK | SRAM7_3_MASK |
147+
SRAM8_MASK | SRAM9_MASK | FWRAM_MASK,
148+
.phy_pwr_gating = LDO_PHY_MASK | USB_PHY_MASK | MIPI_TX_DPHY_MASK | MIPI_RX_DPHY_MASK |
149+
MIPI_PLL_DPHY_MASK,
150+
.vdd_ioflex_3V3 = IOFLEX_LEVEL_3V3,
151+
.vtor_address = SCB->VTOR,
152+
.vtor_address_ns = SCB->VTOR,
153+
.ewic_cfg = EWIC_RTC_A,
154+
.wakeup_events = WE_LPRTC,
155+
};
156+
157+
if (se_services_set_off_profile(&off_profile)) {
158+
MICROPY_BOARD_FATAL_ERROR("se_services_set_off_profile");
159+
}
160+
161+
// Select PLL for PD4 memory.
162+
if (se_services_select_pll_source(PLL_SOURCE_PLL, PLL_TARGET_PD4_SRAM)) {
163+
MICROPY_BOARD_FATAL_ERROR("se_services_select_pll_source");
164+
}
165+
}
166+
167+
MP_WEAK void board_enter_stop(void) {
168+
// Disable NPU interrupt
169+
NVIC_DisableIRQ(NPU_IRQ_NUMBER);
170+
NVIC_ClearPendingIRQ(NPU_IRQ_NUMBER);
171+
172+
// Soft-reset NPU
173+
NPU->RESET = 0x00000000;
174+
175+
// Wait until reset
176+
uint32_t data = 0;
177+
do {
178+
// Poll channel0 status registers
179+
data = NPU->STATUS;
180+
} while (data);
181+
182+
// Set default value, enables off for clocks and power.
183+
NPU->CMD = 0x0000000C;
184+
}
185+
186+
MP_WEAK void board_enter_standby(void) {
187+
188+
}
189+
190+
MP_WEAK void board_exit_standby(void) {
191+
192+
}

‎ports/alif/boards/OPENMV_AE3/board.ld.S‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
#include "mcu/ensemble.ld.S"
2+
3+
/* Define ROMFS partition locations. */
4+
#if CORE_M55_HP
5+
/* The HP core has access to the external OSPI flash and MRAM ROMFS partitions. */
6+
_micropy_hw_romfs_part0_start = 0xa1000000;
7+
_micropy_hw_romfs_part0_size = 16M;
8+
_micropy_hw_romfs_part1_start = ORIGIN(MRAM_FS);
9+
_micropy_hw_romfs_part1_size = LENGTH(MRAM_FS);
10+
#else
11+
/* The HP core has access to the MRAM ROMFS partition. */
12+
_micropy_hw_romfs_part0_start = ORIGIN(MRAM_FS);
13+
_micropy_hw_romfs_part0_size = LENGTH(MRAM_FS);
14+
#endif

‎ports/alif/boards/OPENMV_AE3/mpconfigboard.h‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
#define MICROPY_HW_BOARD_NAME "OpenMV-AE3"
2+
#define MICROPY_HW_MCU_NAME "AE302F80F55D5AE"
3+
4+
#define MICROPY_OBJ_REPR (MICROPY_OBJ_REPR_C)
5+
typedef intptr_t mp_int_t; // must be pointer size
6+
typedef uintptr_t mp_uint_t; // must be pointer size
7+
typedef intptr_t mp_off_t;
8+
9+
#define MICROPY_HW_USB_MSC (CORE_M55_HP)
10+
#define MICROPY_HW_ENABLE_HW_I2C (1)
11+
#define MICROPY_HW_ENABLE_OSPI (CORE_M55_HP)
12+
13+
// ROMFS partitions
14+
#define MICROPY_HW_ROMFS_ENABLE_PART0 (1)
15+
#define MICROPY_HW_ROMFS_ENABLE_PART1 (CORE_M55_HP)
16+
17+
// I2C buses
18+
#define MICROPY_HW_I2C1_SCL (pin_P0_5)
19+
#define MICROPY_HW_I2C1_SDA (pin_P0_4)
20+
21+
#define MICROPY_HW_I2C2_SCL (pin_P5_1)
22+
#define MICROPY_HW_I2C2_SDA (pin_P5_0)
23+
24+
#define MICROPY_HW_I2C3_SCL (pin_P1_1)
25+
#define MICROPY_HW_I2C3_SDA (pin_P1_0)
26+
27+
// SPI buses
28+
#define MICROPY_HW_SPI0_MISO (pin_P5_0)
29+
#define MICROPY_HW_SPI0_MOSI (pin_P5_1)
30+
// #define MICROPY_HW_SPI0_NSS (pin_P5_2)
31+
#define MICROPY_HW_SPI0_SCK (pin_P5_3)
32+
33+
// UART buses
34+
#define MICROPY_HW_UART1_TX (pin_P0_5)
35+
#define MICROPY_HW_UART1_RX (pin_P0_4)
36+
#define MICROPY_HW_UART3_TX (pin_P1_3)
37+
#define MICROPY_HW_UART3_RX (pin_P1_2)
38+
#define MICROPY_HW_UART3_RTS (pin_P7_3)
39+
#define MICROPY_HW_UART3_CTS (pin_P7_2)
40+
#define MICROPY_HW_UART4_TX (pin_P5_1)
41+
#define MICROPY_HW_UART4_RX (pin_P5_0)
42+
#define MICROPY_HW_UART5_TX (pin_P5_3)
43+
#define MICROPY_HW_UART5_RX (pin_P5_2)
44+
45+
#define MICROPY_HW_USB_VID 0x37C5
46+
#define MICROPY_HW_USB_PID 0x16E3
47+
48+
#define MICROPY_HW_USB_MANUFACTURER_STRING "OpenMV"
49+
#define MICROPY_HW_USB_PRODUCT_FS_STRING "OpenMV Camera"
50+
#define MICROPY_HW_USB_MSC_INQUIRY_VENDOR_STRING "OpenMV"
51+
52+
extern void board_startup(void);
53+
#define MICROPY_BOARD_STARTUP board_startup
54+
55+
extern void board_early_init(void);
56+
#define MICROPY_BOARD_EARLY_INIT board_early_init
57+
58+
extern void board_enter_bootloader(void);
59+
#define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) board_enter_bootloader()
60+
61+
extern void board_enter_stop(void);
62+
#define MICROPY_BOARD_ENTER_STOP board_enter_stop
63+
64+
extern void board_enter_standby(void);
65+
#define MICROPY_BOARD_ENTER_STANDBY board_enter_standby
66+
67+
extern void board_exit_standby(void);
68+
#define MICROPY_BOARD_EXIT_STANDBY board_exit_standby
69+
70+
// This is used for alif.Flash() and USB MSC.
71+
#define MICROPY_HW_FLASH_STORAGE_BASE_ADDR (0)
72+
#define MICROPY_HW_FLASH_STORAGE_BYTES (32 * 1024 * 1024)
73+
#define MICROPY_HW_FLASH_STORAGE_FS_BYTES (16 * 1024 * 1024)
74+
#define MICROPY_HW_FLASH_STORAGE_ROMFS_BYTES (16 * 1024 * 1024)
75+
76+
// Murata 1YN configuration
77+
#define CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/w43439_sdio_1yn_7_95_59_combined.h"
78+
#define CYW43_WIFI_NVRAM_INCLUDE_FILE "lib/cyw43-driver/firmware/wifi_nvram_1yn.h"
79+
#define CYW43_BT_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/cyw43_btfw_1yn.h"
80+
#define CYW43_BT_UART_BAUDRATE_DOWNLOAD_FIRMWARE (2000000)
81+
#define CYW43_BT_UART_BAUDRATE_ACTIVE_USE (2000000)
82+
83+
// Bluetooth config
84+
#define MICROPY_HW_BLE_UART_ID (0)
85+
#define MICROPY_HW_BLE_UART_BAUDRATE (115200)

‎ports/alif/boards/OPENMV_AE3/mpconfigboard.mk‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
# TODO: alif_ensemble-cmsis-dfp only supports AE722F80F55D5XX at the moment.
2+
MCU_SERIES = E7
3+
MCU_VARIANT = AE722F80F55D5XX
4+
JLINK_DEV = AE302F80F55D5_HP
5+
LD_FILE = boards/OPENMV_AE3/board.ld.S
6+
PORT = /dev/ttyUSB0
7+
8+
ALIF_TOOLKIT_CFG_PART = AE302F80F55D5AE
9+
ALIF_TOOLKIT_CFG_FILE = \"app-device-config-ae3.json\"
10+
11+
CORE_M55_HP := $(if $(filter M55_HP,$(MCU_CORE)),1,0)
12+
13+
# MicroPython settings
14+
MICROPY_FLOAT_IMPL = float
15+
MICROPY_PY_BLUETOOTH = $(CORE_M55_HP)
16+
MICROPY_BLUETOOTH_NIMBLE = $(CORE_M55_HP)
17+
MICROPY_PY_LWIP = $(CORE_M55_HP)
18+
MICROPY_PY_NETWORK_CYW43 = $(CORE_M55_HP)
19+
MICROPY_PY_SSL = $(CORE_M55_HP)
20+
MICROPY_SSL_MBEDTLS = $(CORE_M55_HP)
21+
MICROPY_PY_OPENAMP = 1
22+
MICROPY_PY_OPENAMP_REMOTEPROC = 1

‎ports/alif/boards/OPENMV_AE3/ospi_xip_user.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
// This file is needed by ospi_xip/source/ospi/ospi_drv.c.
2+
#define OSPI_XIP_ENABLE_AES_DECRYPTION (0)
3+
#define OSPI_XIP_RX_SAMPLE_DELAY (4)
4+
#define OSPI_XIP_DDR_DRIVE_EDGE (0)
5+
// floor(1/4 OSPI clock cycle + 3.6ns) * 2
6+
#define OSPI_XIP_RXDS_DELAY (12)

‎ports/alif/boards/OPENMV_AE3/pins.csv‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
# USB multiplexer
2+
USB_D_SEL,P15_0
3+
USB_D_SEL_FB,P15_1
4+
5+
# LEDs
6+
LED_RED,P0_0
7+
LED_GREEN,P6_3
8+
LED_BLUE,P6_0
9+
10+
# User switch
11+
USR_SW,P15_7
12+
13+
# Flash on OSPI0
14+
FLASH_RESET,P3_3
15+
FLASH_CS,P3_2
16+
FLASH_SCLK_P,P3_0
17+
FLASH_SCLK_N,P3_1
18+
FLASH_DQSM,P1_6
19+
FLASH_D0,P2_0
20+
FLASH_D1,P2_1
21+
FLASH_D2,P2_2
22+
FLASH_D3,P2_3
23+
FLASH_D4,P2_4
24+
FLASH_D5,P2_5
25+
FLASH_D6,P2_6
26+
FLASH_D7,P2_7
27+
28+
# Murata 1YN
29+
BT_UART_RX,P1_4
30+
BT_UART_TX,P1_5
31+
BT_UART_CTS,P6_6
32+
BT_UART_RTS,P6_7
33+
BT_REG_ON,P5_7
34+
BT_DEV_WAKE,P9_2
35+
BT_HOST_WAKE,P13_3
36+
WL_REG_ON,P10_4
37+
WL_HOST_WAKE,P11_0
38+
WL_I2S_SDI,P12_0
39+
WL_I2S_SDO,P12_1
40+
WL_I2S_SCLK,P12_2
41+
WL_I2S_WS,P12_3
42+
WL_IRQ,P9_6
43+
WL_MISO,P12_4
44+
WL_MOSI,P12_5
45+
WL_SCLK,P12_6
46+
WL_CS,P12_7
47+
48+
P0,P5_1
49+
P1,P5_0
50+
P2,P5_3
51+
P3,P5_2
52+
P4,P0_5
53+
P5,P0_4
54+
P6,P7_2
55+
P7,P7_3
56+
P8,P1_2
57+
P9,P1_3
58+
59+
# UART buses
60+
UART1_TX,P0_5
61+
UART1_RX,P0_4
62+
UART3_TX,P1_3
63+
UART3_RX,P1_2
64+
UART3_RTS,P7_3
65+
UART3_CTS,P7_2
66+
UART4_TX,P5_1
67+
UART4_RX,P5_0
68+
UART5_TX,P5_3
69+
UART5_RX,P5_2

0 commit comments

Comments
 (0)