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[clang][test] Update tests for nondeterministic alloca initialization
* Only automatic update tests are effected * Test cxx2a-consteval.cpp required manual updates
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‎clang/test/C/C2x/n2683_2.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,11 @@
88
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
99
// CHECK-NEXT: entry:
1010
// CHECK-NEXT: [[RESULT64:%.*]] = alloca i64, align 8
11+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i64 poison
12+
// CHECK-NEXT: store i64 [[FREEZE_POISON]], ptr [[RESULT64]], align 8
1113
// CHECK-NEXT: [[FLAG_ADD:%.*]] = alloca i8, align 1
14+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze i8 poison
15+
// CHECK-NEXT: store i8 [[FREEZE_POISON1]], ptr [[FLAG_ADD]], align 1
1216
// CHECK-NEXT: store i64 0, ptr [[RESULT64]], align 8
1317
// CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 2147483647, i64 1)
1418
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
@@ -27,7 +31,11 @@ void test_add_overflow_to64() {
2731
// CHECK-SAME: ) #[[ATTR0]] {
2832
// CHECK-NEXT: entry:
2933
// CHECK-NEXT: [[RESULT32:%.*]] = alloca i32, align 4
34+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i32 poison
35+
// CHECK-NEXT: store i32 [[FREEZE_POISON]], ptr [[RESULT32]], align 4
3036
// CHECK-NEXT: [[FLAG_SUB:%.*]] = alloca i8, align 1
37+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze i8 poison
38+
// CHECK-NEXT: store i8 [[FREEZE_POISON1]], ptr [[FLAG_SUB]], align 1
3139
// CHECK-NEXT: store i32 0, ptr [[RESULT32]], align 4
3240
// CHECK-NEXT: [[TMP0:%.*]] = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 2147483647, i32 -1)
3341
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i32, i1 } [[TMP0]], 1
@@ -46,8 +54,14 @@ void test_sub_overflow() {
4654
// CHECK-SAME: ) #[[ATTR0]] {
4755
// CHECK-NEXT: entry:
4856
// CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
57+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i32 poison
58+
// CHECK-NEXT: store i32 [[FREEZE_POISON]], ptr [[A]], align 4
4959
// CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4
60+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze i32 poison
61+
// CHECK-NEXT: store i32 [[FREEZE_POISON1]], ptr [[RESULT]], align 4
5062
// CHECK-NEXT: [[FLAG_MUL:%.*]] = alloca i8, align 1
63+
// CHECK-NEXT: [[FREEZE_POISON2:%.*]] = freeze i8 poison
64+
// CHECK-NEXT: store i8 [[FREEZE_POISON2]], ptr [[FLAG_MUL]], align 1
5165
// CHECK-NEXT: store i32 3, ptr [[A]], align 4
5266
// CHECK-NEXT: store i32 0, ptr [[RESULT]], align 4
5367
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4

‎clang/test/CodeGen/PowerPC/ppc-mma-types.c‎

Lines changed: 98 additions & 82 deletions
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‎clang/test/CodeGen/RISCV/riscv32-vararg.c‎

Lines changed: 193 additions & 173 deletions
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‎clang/test/CodeGen/RISCV/riscv64-vararg.c‎

Lines changed: 43 additions & 35 deletions
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‎clang/test/CodeGen/WebAssembly/wasm-varargs.c‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,14 @@
99
// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4
1010
// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4
1111
// CHECK-NEXT: [[V:%.*]] = alloca i32, align 4
12+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i32 poison
13+
// CHECK-NEXT: store i32 [[FREEZE_POISON]], ptr [[V]], align 4
1214
// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
1315
// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
14-
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
16+
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4, !freeze_bits [[META2:![0-9]+]]
1517
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
1618
// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
17-
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
19+
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4, !freeze_bits [[META2]]
1820
// CHECK-NEXT: store i32 [[TMP0]], ptr [[V]], align 4
1921
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
2022
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[V]], align 4
@@ -37,14 +39,16 @@ int test_i32(char *fmt, ...) {
3739
// CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 4
3840
// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4
3941
// CHECK-NEXT: [[V:%.*]] = alloca i64, align 8
42+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i64 poison
43+
// CHECK-NEXT: store i64 [[FREEZE_POISON]], ptr [[V]], align 8
4044
// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
4145
// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
42-
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
46+
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4, !freeze_bits [[META2]]
4347
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
4448
// CHECK-NEXT: [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
4549
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
4650
// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
47-
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARGP_CUR_ALIGNED]], align 8
51+
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARGP_CUR_ALIGNED]], align 8, !freeze_bits [[META2]]
4852
// CHECK-NEXT: store i64 [[TMP1]], ptr [[V]], align 8
4953
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
5054
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[V]], align 8
@@ -74,10 +78,10 @@ struct S {
7478
// CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 4
7579
// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
7680
// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
77-
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
81+
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4, !freeze_bits [[META2]]
7882
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
7983
// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
80-
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR]], align 4
84+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR]], align 4, !freeze_bits [[META2]]
8185
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP0]], i32 12, i1 false)
8286
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
8387
// CHECK-NEXT: ret void
@@ -103,14 +107,14 @@ struct Z {};
103107
// CHECK-NEXT: [[U:%.*]] = alloca [[STRUCT_Z:%.*]], align 1
104108
// CHECK-NEXT: store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
105109
// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
106-
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
110+
// CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4, !freeze_bits [[META2]]
107111
// CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 0
108112
// CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
109113
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[U]], ptr align 4 [[ARGP_CUR]], i32 0, i1 false)
110-
// CHECK-NEXT: [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
114+
// CHECK-NEXT: [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4, !freeze_bits [[META2]]
111115
// CHECK-NEXT: [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
112116
// CHECK-NEXT: store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
113-
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
117+
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4, !freeze_bits [[META2]]
114118
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[AGG_RESULT]], ptr align 4 [[TMP0]], i32 12, i1 false)
115119
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
116120
// CHECK-NEXT: ret void

‎clang/test/CodeGen/X86/va-arg-sse.c‎

Lines changed: 32 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -14,57 +14,63 @@ struct S a[5];
1414
// CHECK-NEXT: [[P:%.*]] = alloca ptr, align 8
1515
// CHECK-NEXT: [[AP:%.*]] = alloca [1 x %struct.__va_list_tag], align 16
1616
// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4
17+
// CHECK-NEXT: [[FREEZE_POISON:%.*]] = freeze i32 poison
18+
// CHECK-NEXT: store i32 [[FREEZE_POISON]], ptr [[J]], align 4
1719
// CHECK-NEXT: [[K:%.*]] = alloca i32, align 4
20+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze i32 poison
21+
// CHECK-NEXT: store i32 [[FREEZE_POISON1]], ptr [[K]], align 4
1822
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
23+
// CHECK-NEXT: [[FREEZE_POISON2:%.*]] = freeze i32 poison
24+
// CHECK-NEXT: store i32 [[FREEZE_POISON2]], ptr [[I]], align 4
1925
// CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_S]], align 4
2026
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
2127
// CHECK-NEXT: store i32 0, ptr [[J]], align 4
2228
// CHECK-NEXT: store i32 0, ptr [[K]], align 4
2329
// CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[AP]], i64 0, i64 0
2430
// CHECK-NEXT: call void @llvm.va_start.p0(ptr [[ARRAYDECAY]])
2531
// CHECK-NEXT: store ptr getelementptr inbounds ([5 x %struct.S], ptr @a, i64 0, i64 2), ptr [[P]], align 8
26-
// CHECK-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[AP]], i64 0, i64 0
27-
// CHECK-NEXT: [[FP_OFFSET_P:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG:%.*]], ptr [[ARRAYDECAY2]], i32 0, i32 1
28-
// CHECK-NEXT: [[FP_OFFSET:%.*]] = load i32, ptr [[FP_OFFSET_P]], align 4
32+
// CHECK-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[AP]], i64 0, i64 0
33+
// CHECK-NEXT: [[FP_OFFSET_P:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG:%.*]], ptr [[ARRAYDECAY3]], i32 0, i32 1
34+
// CHECK-NEXT: [[FP_OFFSET:%.*]] = load i32, ptr [[FP_OFFSET_P]], align 4, !freeze_bits [[META2:![0-9]+]]
2935
// CHECK-NEXT: [[FITS_IN_FP:%.*]] = icmp ule i32 [[FP_OFFSET]], 144
3036
// CHECK-NEXT: br i1 [[FITS_IN_FP]], label [[VAARG_IN_REG:%.*]], label [[VAARG_IN_MEM:%.*]]
3137
// CHECK: vaarg.in_reg:
32-
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG]], ptr [[ARRAYDECAY2]], i32 0, i32 3
33-
// CHECK-NEXT: [[REG_SAVE_AREA:%.*]] = load ptr, ptr [[TMP0]], align 16
38+
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG]], ptr [[ARRAYDECAY3]], i32 0, i32 3
39+
// CHECK-NEXT: [[REG_SAVE_AREA:%.*]] = load ptr, ptr [[TMP0]], align 16, !freeze_bits [[META2]]
3440
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[REG_SAVE_AREA]], i32 [[FP_OFFSET]]
3541
// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 16
36-
// CHECK-NEXT: [[TMP5:%.*]] = load <2 x float>, ptr [[TMP1]], align 16
37-
// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { <2 x float>, float }, ptr [[TMP]], i32 0, i32 0
38-
// CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[TMP6]], align 4
39-
// CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP2]], align 16
40-
// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds { <2 x float>, float }, ptr [[TMP]], i32 0, i32 1
41-
// CHECK-NEXT: store float [[TMP8]], ptr [[TMP9]], align 4
42-
// CHECK-NEXT: [[TMP11:%.*]] = add i32 [[FP_OFFSET]], 32
43-
// CHECK-NEXT: store i32 [[TMP11]], ptr [[FP_OFFSET_P]], align 4
42+
// CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[TMP1]], align 16, !freeze_bits [[META2]]
43+
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds { <2 x float>, float }, ptr [[TMP]], i32 0, i32 0
44+
// CHECK-NEXT: store <2 x float> [[TMP3]], ptr [[TMP4]], align 4
45+
// CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[TMP2]], align 16, !freeze_bits [[META2]]
46+
// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds { <2 x float>, float }, ptr [[TMP]], i32 0, i32 1
47+
// CHECK-NEXT: store float [[TMP5]], ptr [[TMP6]], align 4
48+
// CHECK-NEXT: [[TMP7:%.*]] = add i32 [[FP_OFFSET]], 32
49+
// CHECK-NEXT: store i32 [[TMP7]], ptr [[FP_OFFSET_P]], align 4
4450
// CHECK-NEXT: br label [[VAARG_END:%.*]]
4551
// CHECK: vaarg.in_mem:
46-
// CHECK-NEXT: [[OVERFLOW_ARG_AREA_P:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG]], ptr [[ARRAYDECAY2]], i32 0, i32 2
47-
// CHECK-NEXT: [[OVERFLOW_ARG_AREA:%.*]] = load ptr, ptr [[OVERFLOW_ARG_AREA_P]], align 8
52+
// CHECK-NEXT: [[OVERFLOW_ARG_AREA_P:%.*]] = getelementptr inbounds [[STRUCT___VA_LIST_TAG]], ptr [[ARRAYDECAY3]], i32 0, i32 2
53+
// CHECK-NEXT: [[OVERFLOW_ARG_AREA:%.*]] = load ptr, ptr [[OVERFLOW_ARG_AREA_P]], align 8, !freeze_bits [[META2]]
4854
// CHECK-NEXT: [[OVERFLOW_ARG_AREA_NEXT:%.*]] = getelementptr i8, ptr [[OVERFLOW_ARG_AREA]], i32 16
4955
// CHECK-NEXT: store ptr [[OVERFLOW_ARG_AREA_NEXT]], ptr [[OVERFLOW_ARG_AREA_P]], align 8
5056
// CHECK-NEXT: br label [[VAARG_END]]
5157
// CHECK: vaarg.end:
5258
// CHECK-NEXT: [[VAARG_ADDR:%.*]] = phi ptr [ [[TMP]], [[VAARG_IN_REG]] ], [ [[OVERFLOW_ARG_AREA]], [[VAARG_IN_MEM]] ]
5359
// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARG]], ptr align 4 [[VAARG_ADDR]], i64 12, i1 false)
54-
// CHECK-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[AP]], i64 0, i64 0
55-
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[ARRAYDECAY3]])
56-
// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[P]], align 8
57-
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne ptr [[TMP15]], null
60+
// CHECK-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], ptr [[AP]], i64 0, i64 0
61+
// CHECK-NEXT: call void @llvm.va_end.p0(ptr [[ARRAYDECAY4]])
62+
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[P]], align 8, !freeze_bits [[META2]]
63+
// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne ptr [[TMP8]], null
5864
// CHECK-NEXT: br i1 [[TOBOOL]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]]
5965
// CHECK: land.lhs.true:
60-
// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[P]], align 8
61-
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP16]], i32 0, i32 0
66+
// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[P]], align 8, !freeze_bits [[META2]]
67+
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP9]], i32 0, i32 0
6268
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x float], ptr [[A]], i64 0, i64 2
63-
// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4
69+
// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !freeze_bits [[META2]]
6470
// CHECK-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARG]], i32 0, i32 0
6571
// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [3 x float], ptr [[A5]], i64 0, i64 2
66-
// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
67-
// CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[TMP17]], [[TMP18]]
72+
// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !freeze_bits [[META2]]
73+
// CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[TMP10]], [[TMP11]]
6874
// CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END]]
6975
// CHECK: if.then:
7076
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
@@ -73,8 +79,8 @@ struct S a[5];
7379
// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
7480
// CHECK-NEXT: br label [[RETURN]]
7581
// CHECK: return:
76-
// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4
77-
// CHECK-NEXT: ret i32 [[TMP19]]
82+
// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[RETVAL]], align 4, !freeze_bits [[META2]]
83+
// CHECK-NEXT: ret i32 [[TMP12]]
7884
//
7985
int check (int z, ...)
8086
{

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