Skip to content

Commit 37616f6

Browse files
jmciverjmciver
committed
[clang][test] Auto update tests for local alloca freeze insertion
1 parent ad9d243 commit 37616f6

File tree

5 files changed

+335
-162
lines changed

5 files changed

+335
-162
lines changed

‎clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c‎

Lines changed: 34 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,16 +18,22 @@
1818
// CHECK-NEXT: store ptr [[FREEZE_POISON]], ptr [[VQP]], align 8
1919
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
2020
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VQP]], align 8
21+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze <512 x i1> poison
22+
// CHECK-NEXT: store <512 x i1> [[FREEZE_POISON1]], ptr [[VQ1]], align 64
2123
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8
2224
// CHECK-NEXT: [[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64, !freeze_bits [[META2:![0-9]+]]
2325
// CHECK-NEXT: store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64
26+
// CHECK-NEXT: [[FREEZE_POISON2:%.*]] = freeze <512 x i1> poison
27+
// CHECK-NEXT: store <512 x i1> [[FREEZE_POISON2]], ptr [[VQ2]], align 64
2428
// CHECK-NEXT: [[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
2529
// CHECK-NEXT: store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64
30+
// CHECK-NEXT: [[FREEZE_POISON3:%.*]] = freeze <512 x i1> poison
31+
// CHECK-NEXT: store <512 x i1> [[FREEZE_POISON3]], ptr [[VQ3]], align 64
2632
// CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
2733
// CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
2834
// CHECK-NEXT: [[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]])
2935
// CHECK-NEXT: store <512 x i1> [[TMP6]], ptr [[VQ3]], align 64
30-
// CHECK-NEXT: [[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64, !freeze_bits [[META2]]
36+
// CHECK-NEXT: [[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64
3137
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VQP]], align 8
3238
// CHECK-NEXT: store <512 x i1> [[TMP7]], ptr [[TMP8]], align 64
3339
// CHECK-NEXT: ret void
@@ -46,16 +52,22 @@
4652
// CHECK-BE-NEXT: store ptr [[FREEZE_POISON]], ptr [[VQP]], align 8
4753
// CHECK-BE-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
4854
// CHECK-BE-NEXT: store ptr [[TMP0]], ptr [[VQP]], align 8
55+
// CHECK-BE-NEXT: [[FREEZE_POISON1:%.*]] = freeze <512 x i1> poison
56+
// CHECK-BE-NEXT: store <512 x i1> [[FREEZE_POISON1]], ptr [[VQ1]], align 64
4957
// CHECK-BE-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8
5058
// CHECK-BE-NEXT: [[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64, !freeze_bits [[META2:![0-9]+]]
5159
// CHECK-BE-NEXT: store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64
60+
// CHECK-BE-NEXT: [[FREEZE_POISON2:%.*]] = freeze <512 x i1> poison
61+
// CHECK-BE-NEXT: store <512 x i1> [[FREEZE_POISON2]], ptr [[VQ2]], align 64
5262
// CHECK-BE-NEXT: [[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
5363
// CHECK-BE-NEXT: store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64
64+
// CHECK-BE-NEXT: [[FREEZE_POISON3:%.*]] = freeze <512 x i1> poison
65+
// CHECK-BE-NEXT: store <512 x i1> [[FREEZE_POISON3]], ptr [[VQ3]], align 64
5466
// CHECK-BE-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
5567
// CHECK-BE-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
5668
// CHECK-BE-NEXT: [[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]])
5769
// CHECK-BE-NEXT: store <512 x i1> [[TMP6]], ptr [[VQ3]], align 64
58-
// CHECK-BE-NEXT: [[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64, !freeze_bits [[META2]]
70+
// CHECK-BE-NEXT: [[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64
5971
// CHECK-BE-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VQP]], align 8
6072
// CHECK-BE-NEXT: store <512 x i1> [[TMP7]], ptr [[TMP8]], align 64
6173
// CHECK-BE-NEXT: ret void
@@ -85,9 +97,13 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
8597
// CHECK-NEXT: store ptr [[FREEZE_POISON]], ptr [[VPP]], align 8
8698
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
8799
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VPP]], align 8
100+
// CHECK-NEXT: [[FREEZE_POISON1:%.*]] = freeze <256 x i1> poison
101+
// CHECK-NEXT: store <256 x i1> [[FREEZE_POISON1]], ptr [[VP1]], align 32
88102
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VPP]], align 8
89103
// CHECK-NEXT: [[TMP2:%.*]] = load <256 x i1>, ptr [[TMP1]], align 32, !freeze_bits [[META2]]
90104
// CHECK-NEXT: store <256 x i1> [[TMP2]], ptr [[VP1]], align 32
105+
// CHECK-NEXT: [[FREEZE_POISON2:%.*]] = freeze <256 x i1> poison
106+
// CHECK-NEXT: store <256 x i1> [[FREEZE_POISON2]], ptr [[VP2]], align 32
91107
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
92108
// CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
93109
// CHECK-NEXT: [[TMP5:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
@@ -96,11 +112,15 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
96112
// CHECK-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
97113
// CHECK-NEXT: [[TMP8:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP7]], <16 x i8> [[TMP6]])
98114
// CHECK-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
99-
// CHECK-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32, !freeze_bits [[META2]]
115+
// CHECK-NEXT: [[FREEZE_POISON3:%.*]] = freeze <256 x i1> poison
116+
// CHECK-NEXT: store <256 x i1> [[FREEZE_POISON3]], ptr [[VP3]], align 32
117+
// CHECK-NEXT: [[FREEZE_POISON4:%.*]] = freeze <512 x i1> poison
118+
// CHECK-NEXT: store <512 x i1> [[FREEZE_POISON4]], ptr [[VQ]], align 64
119+
// CHECK-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
100120
// CHECK-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
101121
// CHECK-NEXT: [[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]])
102122
// CHECK-NEXT: store <512 x i1> [[TMP11]], ptr [[VQ]], align 64
103-
// CHECK-NEXT: [[TMP12:%.*]] = load <256 x i1>, ptr [[VP3]], align 32, !freeze_bits [[META2]]
123+
// CHECK-NEXT: [[TMP12:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
104124
// CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VPP]], align 8
105125
// CHECK-NEXT: store <256 x i1> [[TMP12]], ptr [[TMP13]], align 32
106126
// CHECK-NEXT: ret void
@@ -120,9 +140,13 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
120140
// CHECK-BE-NEXT: store ptr [[FREEZE_POISON]], ptr [[VPP]], align 8
121141
// CHECK-BE-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
122142
// CHECK-BE-NEXT: store ptr [[TMP0]], ptr [[VPP]], align 8
143+
// CHECK-BE-NEXT: [[FREEZE_POISON1:%.*]] = freeze <256 x i1> poison
144+
// CHECK-BE-NEXT: store <256 x i1> [[FREEZE_POISON1]], ptr [[VP1]], align 32
123145
// CHECK-BE-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VPP]], align 8
124146
// CHECK-BE-NEXT: [[TMP2:%.*]] = load <256 x i1>, ptr [[TMP1]], align 32, !freeze_bits [[META2]]
125147
// CHECK-BE-NEXT: store <256 x i1> [[TMP2]], ptr [[VP1]], align 32
148+
// CHECK-BE-NEXT: [[FREEZE_POISON2:%.*]] = freeze <256 x i1> poison
149+
// CHECK-BE-NEXT: store <256 x i1> [[FREEZE_POISON2]], ptr [[VP2]], align 32
126150
// CHECK-BE-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
127151
// CHECK-BE-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
128152
// CHECK-BE-NEXT: [[TMP5:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
@@ -131,11 +155,15 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
131155
// CHECK-BE-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
132156
// CHECK-BE-NEXT: [[TMP8:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP6]], <16 x i8> [[TMP7]])
133157
// CHECK-BE-NEXT: store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
134-
// CHECK-BE-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32, !freeze_bits [[META2]]
158+
// CHECK-BE-NEXT: [[FREEZE_POISON3:%.*]] = freeze <256 x i1> poison
159+
// CHECK-BE-NEXT: store <256 x i1> [[FREEZE_POISON3]], ptr [[VP3]], align 32
160+
// CHECK-BE-NEXT: [[FREEZE_POISON4:%.*]] = freeze <512 x i1> poison
161+
// CHECK-BE-NEXT: store <512 x i1> [[FREEZE_POISON4]], ptr [[VQ]], align 64
162+
// CHECK-BE-NEXT: [[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
135163
// CHECK-BE-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
136164
// CHECK-BE-NEXT: [[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]])
137165
// CHECK-BE-NEXT: store <512 x i1> [[TMP11]], ptr [[VQ]], align 64
138-
// CHECK-BE-NEXT: [[TMP12:%.*]] = load <256 x i1>, ptr [[VP3]], align 32, !freeze_bits [[META2]]
166+
// CHECK-BE-NEXT: [[TMP12:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
139167
// CHECK-BE-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VPP]], align 8
140168
// CHECK-BE-NEXT: store <256 x i1> [[TMP12]], ptr [[TMP13]], align 32
141169
// CHECK-BE-NEXT: ret void

0 commit comments

Comments
 (0)