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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server < %s | FileCheck %s |
| 3 | + |
| 4 | +@dequant_coef = external constant [6 x [4 x [4 x i32]]] |
| 5 | + |
| 6 | +define fastcc i32 @test(ptr %0, i16 %1, i32 %2) { |
| 7 | +; CHECK-LABEL: define fastcc i32 @test( |
| 8 | +; CHECK-SAME: ptr [[TMP0:%.*]], i16 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] { |
| 9 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 10 | +; CHECK-NEXT: [[CONV_2:%.*]] = zext i16 [[TMP1]] to i32 |
| 11 | +; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2 |
| 12 | +; CHECK-NEXT: [[ADD68:%.*]] = add i32 [[TMP2]], 1 |
| 13 | +; CHECK-NEXT: [[CONV_3_1:%.*]] = zext i16 [[TMP3]] to i32 |
| 14 | +; CHECK-NEXT: [[ADD68_1:%.*]] = add i32 [[CONV_3_1]], -1 |
| 15 | +; CHECK-NEXT: [[ADD118_1:%.*]] = or i32 [[ADD68]], [[ADD68_1]] |
| 16 | +; CHECK-NEXT: [[CMP16_I:%.*]] = icmp slt i32 [[ADD118_1]], 0 |
| 17 | +; CHECK-NEXT: [[SUB2_I2:%.*]] = sub i32 0, [[TMP2]] |
| 18 | +; CHECK-NEXT: [[ADD56_1:%.*]] = or i32 [[TMP2]], [[CONV_3_1]] |
| 19 | +; CHECK-NEXT: [[ADD37_1:%.*]] = add i32 [[CONV_2]], 1 |
| 20 | +; CHECK-NEXT: [[MUL137:%.*]] = shl i32 [[ADD56_1]], 1 |
| 21 | +; CHECK-NEXT: [[SUB138:%.*]] = sub i32 [[ADD37_1]], [[MUL137]] |
| 22 | +; CHECK-NEXT: [[CMP16_I45:%.*]] = icmp slt i32 [[SUB138]], 0 |
| 23 | +; CHECK-NEXT: [[SUB2_I44:%.*]] = sub i32 0, [[ADD56_1]] |
| 24 | +; CHECK-NEXT: [[RETVAL_0_I46:%.*]] = select i1 [[CMP16_I45]], i32 [[SUB2_I44]], i32 0 |
| 25 | +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 12), align 4 |
| 26 | +; CHECK-NEXT: [[MUL175_3635:%.*]] = mul i32 [[RETVAL_0_I46]], [[TMP4]] |
| 27 | +; CHECK-NEXT: [[RETVAL_0_I:%.*]] = select i1 [[CMP16_I]], i32 [[SUB2_I2]], i32 0 |
| 28 | +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 16), align 16 |
| 29 | +; CHECK-NEXT: [[MUL175_1:%.*]] = mul i32 [[RETVAL_0_I]], [[TMP5]] |
| 30 | +; CHECK-NEXT: [[ADD300:%.*]] = or i32 [[MUL175_3635]], [[MUL175_1]] |
| 31 | +; CHECK-NEXT: ret i32 [[ADD300]] |
| 32 | +; |
| 33 | +entry: |
| 34 | + %conv.2 = zext i16 %1 to i32 |
| 35 | + %3 = load i16, ptr %0, align 2 |
| 36 | + %add68 = add i32 %2, 1 |
| 37 | + %conv.3.1 = zext i16 %3 to i32 |
| 38 | + %add68.1 = add i32 %conv.3.1, -1 |
| 39 | + %add118.1 = or i32 %add68, %add68.1 |
| 40 | + %cmp16.i = icmp slt i32 %add118.1, 0 |
| 41 | + %sub2.i2 = sub i32 0, %2 |
| 42 | + %add56.1 = or i32 %2, %conv.3.1 |
| 43 | + %add37.1 = add i32 %conv.2, 1 |
| 44 | + %mul137 = shl i32 %add56.1, 1 |
| 45 | + %sub138 = sub i32 %add37.1, %mul137 |
| 46 | + %cmp16.i45 = icmp slt i32 %sub138, 0 |
| 47 | + %sub2.i44 = sub i32 0, %add56.1 |
| 48 | + %retval.0.i46 = select i1 %cmp16.i45, i32 %sub2.i44, i32 0 |
| 49 | + %4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 12), align 4 |
| 50 | + %mul175.3635 = mul i32 %retval.0.i46, %4 |
| 51 | + %retval.0.i = select i1 %cmp16.i, i32 %sub2.i2, i32 0 |
| 52 | + %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 16), align 16 |
| 53 | + %mul175.1 = mul i32 %retval.0.i, %5 |
| 54 | + %add300 = or i32 %mul175.3635, %mul175.1 |
| 55 | + ret i32 %add300 |
| 56 | +} |
| 57 | + |
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