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[RISCV] Move RISCVInsertVSETVLI to after phi elimination (llvm#91440)
Split off from llvm#70549, this patch moves RISCVInsertVSETVLI to after phi elimination where we exit SSA and need to move to LiveVariables. The motivation for splitting this off is to avoid the large scheduling diffs from moving completely to after regalloc, and instead focus on converting the pass to work on LiveIntervals. The two main changes required are updating VSETVLIInfo to store VNInfos instead of MachineInstrs, which allows us to still check for PHI defs in needVSETVLIPHI, and fixing up the live intervals of any AVL operands after inserting new instructions. On O3 the pass is inserted after the register coalescer, otherwise we end up with a bunch of COPYs around eliminated PHIs that trip up needVSETVLIPHI. Co-authored-by: Piyou Chen <[email protected]>
1 parent 72b2c37 commit 1a58e88

29 files changed

+312
-261
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 166 additions & 96 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -541,9 +541,16 @@ void RISCVPassConfig::addPreRegAlloc() {
541541
addPass(createRISCVPreRAExpandPseudoPass());
542542
if (TM->getOptLevel() != CodeGenOptLevel::None)
543543
addPass(createRISCVMergeBaseOffsetOptPass());
544+
544545
addPass(createRISCVInsertReadWriteCSRPass());
545546
addPass(createRISCVInsertWriteVXRMPass());
546-
addPass(createRISCVInsertVSETVLIPass());
547+
548+
// Run RISCVInsertVSETVLI after PHI elimination. On O1 and above do it after
549+
// register coalescing so needVSETVLIPHI doesn't need to look through COPYs.
550+
if (TM->getOptLevel() == CodeGenOptLevel::None)
551+
insertPass(&PHIEliminationID, createRISCVInsertVSETVLIPass());
552+
else
553+
insertPass(&RegisterCoalescerID, createRISCVInsertVSETVLIPass());
547554
}
548555

549556
void RISCVPassConfig::addFastRegAlloc() {

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,12 +42,14 @@
4242
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
4343
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
4444
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
45-
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4645
; CHECK-NEXT: Init Undef Pass
4746
; CHECK-NEXT: Eliminate PHI nodes for register allocation
47+
; CHECK-NEXT: MachineDominator Tree Construction
48+
; CHECK-NEXT: Slot index numbering
49+
; CHECK-NEXT: Live Interval Analysis
50+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4851
; CHECK-NEXT: Two-Address instruction pass
4952
; CHECK-NEXT: Fast Register Allocator
50-
; CHECK-NEXT: MachineDominator Tree Construction
5153
; CHECK-NEXT: Slot index numbering
5254
; CHECK-NEXT: Live Interval Analysis
5355
; CHECK-NEXT: RISC-V Coalesce VSETVLI pass

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,6 @@
117117
; CHECK-NEXT: RISC-V Merge Base Offset
118118
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
119119
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
120-
; CHECK-NEXT: RISC-V Insert VSETVLI pass
121120
; CHECK-NEXT: Detect Dead Lanes
122121
; CHECK-NEXT: Init Undef Pass
123122
; CHECK-NEXT: Process Implicit Definitions
@@ -129,6 +128,7 @@
129128
; CHECK-NEXT: Slot index numbering
130129
; CHECK-NEXT: Live Interval Analysis
131130
; CHECK-NEXT: Register Coalescer
131+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
132132
; CHECK-NEXT: Rename Disconnected Subregister Components
133133
; CHECK-NEXT: Machine Instruction Scheduler
134134
; CHECK-NEXT: Machine Block Frequency Analysis

‎llvm/test/CodeGen/RISCV/rvv/combine-vmv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ define <vscale x 4 x i32> @vadd_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32>
3636
define <vscale x 4 x i32> @vadd_same_passthru(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
3737
; CHECK-LABEL: vadd_same_passthru:
3838
; CHECK: # %bb.0:
39-
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
4039
; CHECK-NEXT: vmv2r.v v14, v8
40+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
4141
; CHECK-NEXT: vadd.vv v14, v10, v12
4242
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
4343
; CHECK-NEXT: vmv.v.v v8, v14

‎llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,8 @@ define void @constant_zero_stride(ptr %s, ptr %d) {
149149
; CHECK: # %bb.0:
150150
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
151151
; CHECK-NEXT: vle8.v v8, (a0)
152-
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
153152
; CHECK-NEXT: vmv1r.v v9, v8
153+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
154154
; CHECK-NEXT: vslideup.vi v9, v8, 2
155155
; CHECK-NEXT: vse8.v v9, (a1)
156156
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,9 +141,9 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
141141
; SINK-NEXT: andi a4, a3, 1024
142142
; SINK-NEXT: xori a3, a4, 1024
143143
; SINK-NEXT: slli a5, a5, 1
144-
; SINK-NEXT: vsetvli a6, zero, e32, m2, ta, ma
145144
; SINK-NEXT: mv a6, a0
146145
; SINK-NEXT: mv a7, a3
146+
; SINK-NEXT: vsetvli t0, zero, e32, m2, ta, ma
147147
; SINK-NEXT: .LBB1_3: # %vector.body
148148
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
149149
; SINK-NEXT: vl2re32.v v8, (a6)
@@ -183,9 +183,9 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
183183
; DEFAULT-NEXT: andi a4, a3, 1024
184184
; DEFAULT-NEXT: xori a3, a4, 1024
185185
; DEFAULT-NEXT: slli a5, a5, 1
186-
; DEFAULT-NEXT: vsetvli a6, zero, e32, m2, ta, ma
187186
; DEFAULT-NEXT: mv a6, a0
188187
; DEFAULT-NEXT: mv a7, a3
188+
; DEFAULT-NEXT: vsetvli t0, zero, e32, m2, ta, ma
189189
; DEFAULT-NEXT: .LBB1_3: # %vector.body
190190
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
191191
; DEFAULT-NEXT: vl2re32.v v8, (a6)
@@ -459,9 +459,9 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
459459
; SINK-NEXT: addi a3, a2, -1
460460
; SINK-NEXT: andi a4, a3, 1024
461461
; SINK-NEXT: xori a3, a4, 1024
462-
; SINK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
463462
; SINK-NEXT: mv a5, a0
464463
; SINK-NEXT: mv a6, a3
464+
; SINK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
465465
; SINK-NEXT: .LBB4_3: # %vector.body
466466
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
467467
; SINK-NEXT: vl1re32.v v8, (a5)
@@ -500,9 +500,9 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
500500
; DEFAULT-NEXT: addi a3, a2, -1
501501
; DEFAULT-NEXT: andi a4, a3, 1024
502502
; DEFAULT-NEXT: xori a3, a4, 1024
503-
; DEFAULT-NEXT: vsetvli a5, zero, e32, m1, ta, ma
504503
; DEFAULT-NEXT: mv a5, a0
505504
; DEFAULT-NEXT: mv a6, a3
505+
; DEFAULT-NEXT: vsetvli a7, zero, e32, m1, ta, ma
506506
; DEFAULT-NEXT: .LBB4_3: # %vector.body
507507
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
508508
; DEFAULT-NEXT: vl1re32.v v8, (a5)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1155,8 +1155,8 @@ define void @mulhu_v8i16(ptr %x) {
11551155
; CHECK-NEXT: vle16.v v8, (a0)
11561156
; CHECK-NEXT: vmv.v.i v9, 0
11571157
; CHECK-NEXT: lui a1, 1048568
1158-
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
11591158
; CHECK-NEXT: vmv.v.i v10, 0
1159+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
11601160
; CHECK-NEXT: vmv.s.x v10, a1
11611161
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
11621162
; CHECK-NEXT: vmv.v.i v11, 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12092,8 +12092,8 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
1209212092
; RV64V: # %bb.0:
1209312093
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
1209412094
; RV64V-NEXT: vsext.vf8 v16, v8
12095-
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
1209612095
; RV64V-NEXT: vmv1r.v v12, v10
12096+
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
1209712097
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
1209812098
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
1209912099
; RV64V-NEXT: vslidedown.vi v10, v10, 16

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -369,8 +369,8 @@ define <4 x i8> @vslide1up_4xi8_neg_incorrect_insert3(<4 x i8> %v, i8 %b) {
369369
define <2 x i8> @vslide1up_4xi8_neg_length_changing(<4 x i8> %v, i8 %b) {
370370
; CHECK-LABEL: vslide1up_4xi8_neg_length_changing:
371371
; CHECK: # %bb.0:
372-
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
373372
; CHECK-NEXT: vmv1r.v v9, v8
373+
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
374374
; CHECK-NEXT: vmv.s.x v9, a0
375375
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
376376
; CHECK-NEXT: vslideup.vi v9, v8, 1

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